The APC’s blueprint for silicon photonics

The Advanced Photonics Coalition (APC) wants to smooth the path for silicon photonics to become a high-volume manufacturing technology.

Jeffery Maki

The organisation is talking to companies to tackle issues whose solutions will benefit the photonics technology.

The Advanced Photonics Coalition wants to act as an industry catalyst to prove technologies and reduce the risk associated with their development, says Jeffery Maki, Distinguished Engineer at Juniper Networks and a member of the Advanced Photonics Coalition's board.

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The various paths to co-packaged optics

Near package optics has emerged as companies have encountered the complexities of co-packaged optics. It should not be viewed as an alternative to co-packaged optics but rather a pragmatic approach for its implementation.

Co-packaged optics will be one of several hot topics at the upcoming OFC show in March.

Placing optics next to silicon is seen as the only way to meet the future input-output (I/O) requirements of ICs such as Ethernet switches and high-end processors.

Brad Booth

For now, pluggable optics do the job of routing traffic between Ethernet switch chips in the data centre. The pluggable modules sit on the switch platform’s front panel at the edge of the printed circuit board (PCB) hosting the switch chip.

But with switch silicon capacity doubling every two years, engineers are being challenged to get data into and out of the chip while ensuring power consumption does not rise.

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Broadcom discusses its co-packaged optics plans

If electrical interfaces are becoming an impediment, is co-packaged optics the answer? Broadcom certainly thinks so.

One reason for the growing interest in co-packaged optics is the input-output (I/O) demands of switch chips. If the packet processing capacity of such chips is doubling every two years, their I/O must double too.

Alexis BjörlinRepeatedly doubling the data throughput of a switch chip is a challenge.

Each new generation of switch chip must either double the number of serialiser-deserialiser (serdes) circuits or double their speed.

A higher serdes count - the latest 25.6-terabit switch ICs have 256, 100 gigabit-per-second serdes - requires more silicon area while both approaches - a higher count and higher speed - increase the chip's power consumption.

Faster electrical interfaces also complicate the system design since moving the data between the chip and the optical modules on the switch's front panel becomes more challenging.

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COBO adds co-packaged optics to its agenda

The Consortium of On-Board Optics (COBO) is progressing with its work to create specifications for co-packaged optics.

The decision to address co-packaged optics by an organisation established to promote on-board optics reflects the significant industry interest co-packaged optics has gained in the last year.

So says Brad Booth, director, leading edge architecture pathfinding team in Azure hardware systems and infrastructure at Microsoft.

Source: COBO

The COBO work also complements that of the OIF which has set up its own co-packaged optics framework. 

“We have a different collection of members [to the OIF],” says Booth. “Our members are very strong on optical connectivity and materials whereas the OIF is known for its electrical interface work and module activities like 400ZR.”

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The compound complexity of co-packaged optics

Part 1: The OIF’s co-packaging initiative

Large-scale data centres consume huge amounts of power; one building on a data centre campus can consume 100MW. But there is a limit as to the overall power that can be supplied.

Jeff Hutchins

The challenge facing data centre operators is that networking, used to link the equipment inside the data centre, continues to consume more and more power.

That means less power remains for the servers; the compute that does the revenue-generating work.

This is forcing a rethink regarding networking and explains the growing interest in co-packaged optics, a technique that effectively adds optical input-output (I/O) to a chip.

Two industry organisations - the OIF and The Consortium for On-Board Optics (COBO) - have each started work to identify the requirements needed for co-packaged optics adoption.

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Silicon photonics webinar

Daryl Inniss and I assess how the technology and marketplace has changed since we published our silicon photonics book at the end of 2016. Click here to view the webinar. Ours is the first of a series of webinars that COBO, the Consortium of On-Board Optics, is hosting.

And here is a copy of the slides, click here.

Intel combines optics to its Tofino 2 switch chip

Part 1: Co-packaged Ethernet switch 

The advent of co-packaged optics has moved a step closer with Intel’s demonstration of a 12.8-terabit Ethernet switch chip with optical input-output (I/O).  

Source: Intel.

The design couples a Barefoot Tofino 2 switch chip to up to 16 optical ‘tiles’ - each tile, a 1.6-terabit silicon photonics die - for a total I/O of 25.6 terabits.

“It’s an easy upgrade to add our next-generation 25.6-terabit [switch chip] which is coming shortly,” says Ed Doe, Intel’s vice president, connectivity group, general manager, Barefoot division. 

Intel acquired switch-chip maker, Barefoot, seven months ago after which it started the co-packaging optics project.

Intel also revealed that it is in the process of qualifying four new optical transceivers - a 400Gbase-DR4, a 200-gigabit FR4, a 100-gigabit FR1 and a 100Gbase-LR4 - to add to its portfolio of 100-gigabit PSM4 and CWDM4 modules.

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