Broadcom discusses its co-packaged optics plans

If electrical interfaces are becoming an impediment, is co-packaged optics the answer? Broadcom certainly thinks so.

One reason for the growing interest in co-packaged optics is the input-output (I/O) demands of switch chips. If the packet processing capacity of such chips is doubling every two years, their I/O must double too.

Alexis BjörlinRepeatedly doubling the data throughput of a switch chip is a challenge.

Each new generation of switch chip must either double the number of serialiser-deserialiser (serdes) circuits or double their speed.

A higher serdes count - the latest 25.6-terabit switch ICs have 256, 100 gigabit-per-second serdes - requires more silicon area while both approaches - a higher count and higher speed - increase the chip's power consumption.

Faster electrical interfaces also complicate the system design since moving the data between the chip and the optical modules on the switch's front panel becomes more challenging.

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Co-packaged optics to debut with 25.6 terabit switch chips

The second article in a series on co-packaged optics.

Part 2: Broadcom - a switch-chip vendor 

The hyperscalers require ever more switching capacity in their data centres to scale the applications they run. A hierarchy of connected switches fitted with optical interfaces is used to provide the pathways that link the tens of thousands of servers found in data centres.

Silicon vendors are responding to this need by doubling the capacity of their switch chips every two years. The largest switch chips have a 12.8-terabit capacity and the first 25.6-terabit devices are expected next year. This relentless pace, however, is one that the optical module makers are struggling to match. 

Source: Gazettabyte

“It is a problem for the optics industry,” says Robert Stone, Distinguished Engineer at leading switch chip player, Broadcom. “The cadence at which we can evolve silicon generally moves a lot faster than the optics guys can monetise a generation of investment, and then reinvest it.”

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Ayar Labs prepares for the era of co-packaged optics

The first of two articles on co-packaged optics.

Part 1: Ayar Labs

Ayar Labs is readying its co-packaged optics technology for scaled production in the second half of 2020. So says CEO Charlie Wuischpard who joined the start-up in late 2018 after it secured $24 million in funding to bring its products to market.

Co-packaged optics refers to the intimate coupling of optics with an ASIC in one package. Such tightly-coupled optics promises to overcome the growing system challenges associated with linking an ASIC’s high-speed signals to pluggable optics residing on a platform’s faceplate.

Charlie Wuischpard Wuischpard joined Ayar Labs from Intel where he led the supercomputing segment within the company’s data centre group. Wuischpard also led Intel’s disaggregated rack initiative.

“In both these, silicon photonics plays a huge role in enabling future architectures and future designs,” he says.

Ayar Labs raised its funding after demonstrating successfully its optical designs: a silicon-photonics optical chiplet, dubbed Teraphy, and its Supernova external laser source. 

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