Intel's 100-gigabit silicon photonics move

Intel has unveiled two 100-gigabit optical modules for the data centre made using silicon photonics technology.

Alexis Bjorlin

The PSM4 and CWDM4/CLR4 100-gigabit modules mark the first commercial application of a hybrid integration technique for silicon photonics, dubbed heterogeneous integration, that Intel has been developing for years.

Intel's 100-gigabit module announcement follows the news that Juniper Networks has entered into an agreement to acquire start-up, Aurrion, for $165 million. Aurrion is another silicon photonics player developing this hybrid integration technology for its products. 

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Juniper Networks to acquire Aurrion for $165 million

The announcement of the acquisition was low key. A CTO blog post and a statement that Juniper Networks had entered into an agreement to acquire Aurrion, the fabless silicon photonics start-up. No fee was mentioned.

However, in the company's US Securities and Exchange Commission filing, Juniper values the deal at approximately $165 million. "The Company believes the acquisition will help to fuel its long-term competitive advantage by enabling cost-effective, high-density, high-speed optical networks," it said. The deal is expected to be closed this quarter.

Source: Gazettabyte

At first glance, Juniper is simply the latest in a series of systems vendors bringing silicon photonics in-house. Silicon photonics is a technology that allows photonic devices to be made on a silicon substrate, fabricated in a CMOS facility.

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The ecosystem for silicon photonics starts to take shape

Silicon photonics luminaries series

Interview 6: imec - Philippe Absil and Joris Van Campenhout

Imec has a unique vantage point when it comes to the status and direction of silicon photonics.  

The Belgium nano-electronics research centre gets to see prototype designs nearing commercialisation due to its silicon photonics integration platform and foundry service. “We allow companies to build prototypes using a robust silicon photonics technology,” says Philippe Absil, department director for 3D and optical technologies at imec.

Philippe Absil

Imec also works intimately with several partners on longer-term research, one being Huawei. This optical I/O R&D activity is part of imec’s CORE CMOS scaling R&D programme which as well as Huawei includes GlobalFoundries, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony and TSMC. The research is sufficiently far ahead to be deemed pre-competitive such that all the firms collaborate. 

For silicon photonics, the optical I/O research includes optical integration schemes, new device concepts and new materials. “The aim is to bring silicon photonics technology to the next level in order to resolve today’s challenges,” says Absil.  

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OIF starts work on a terabit-plus CFP8-ACO module

The Optical Internetworking Forum (OIF) has started a new analogue coherent optics (ACO) specification based on the CFP8 pluggable module.

The CFP8 is the latest is a series of optical modules specified by the CFP Multi-Source Agreement and will support the emerging 400 Gigabit Ethernet standard.

Karl GassAn ACO module used for optical transport integrates the optics and driver electronics while the accompanying coherent DSP-ASIC residing on the line card.

Systems vendors can thus use their own DSP-ASIC, or a merchant one if they don’t have an in-house design, while choosing the coherent optics from various module makers. The optics and the DSP-ASIC communicate via a high-speed electrical connector on the line card.

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ST makes its first PSM4 optical engine deliveries

Flavio Benetti is upbeat about the prospects of silicon photonics. “Silicon photonics as a market is at a turning point this year,” he says.

What gives Benetti confidence is the demand he is seeing for 100-gigabit transceivers in the data centre. “From my visibility today, the tipping point is 2016,” says Benetti, group vice president and general manager, digital and mixed processes ASIC division at STMicroelectronics.

Flavio Benetti

Benetti and colleagues at ST have spent the last four years working to bring to market the silicon photonics technology that the chip company licensed from Luxtera.

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Verizon's move to become a digital service provider

Verizon’s next-generation network based on network functions virtualisation (NFV) and software-defined networking (SDN) is rapidly taking shape.

Working with Dell, Big Switch Networks and Red Hat, the US telco announced in April it had already brought online five data centres. Since then it has deployed more sites but is not saying how many.

Source: Verizon

“We are laying the foundation of the programmable infrastructure that will allow us to do all the automation, virtualisation and the software-defining we want to do on top of that,” says Chris Emmons, director, network infrastructure planning at Verizon.

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FPGAs with 56-gigabit transceivers set for 2017

Xilinx is expected to ship its first FPGAs featuring 56-gigabit transceivers next year. 

The company demonstrated a 56-gigabit transceiver using 4-level pulse-amplitude modulation (PAM-4) at the recent OFC show. The 56-gigabit transceiver, also referred to as a serialiser-deserialiser (serdes), was shown successfully working over backplane specified for 25-gigabit signalling only.

Gilles GarciaXilinx's 56-gigabit serdes is implemented using a 16nm CMOS process node but the first FPGAs featuring the design will be made using a 7nm process. Gilles Garcia says the choice of 7nm CMOS is solely a business decision and not a technical one.

”Optical module [makers] will take another year to make something decent using PAM-4," says Garcia, Xilinx's director marketing and business development, wired communications. "Our 7nm FPGAs will follow very soon afterwards.”

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