Compute vendors set to drive optical I/O innovation

Part 2: Data centre and high-performance computing trends

Professor Vladimir Stojanovic has an engaging mix of roles.

When he is not a professor of electrical engineering and computer science at the University of California, Berkeley, he is the chief architect at optical interconnect start-up, Ayar Labs.

Professor Vladimir Stojanovic

Until recently Stojanovic spent four days each week at Ayar Labs. But last year, more of his week was spent at Berkeley.

Stojanovic is a co-author of a 2015 Nature paper that detailed a monolithic electronic-photonics technology. The paper described a technological first: how a RISC-V processor communicated with the outside world using optical rather than electronic interfaces. 

It is this technology that led to the founding of Ayar Labs.

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Books read in 2021: Part 3

In Part III, two more industry figures pick their reads of the year: Dana Cooperson of Blue Heliotrope Research and ADVA's Gareth Spence. 

Dana Cooperson, Founder and Principal Analyst at Blue Heliotrope Research

My reading traverses different ground from that of other invited analysts to this yearly section. In addition, my ‘avoid new releases’ approach means my picks are not from 2021. And before jumping straight into recommendations, I’ll preface my comments with an homage to communal aspects of reading that have meant so much to me, especially during these two Covid years.

My two book groups managed to meet steadily during the pandemic, sometimes while sitting outside in the snow, covered with blankets and sipping hot tea.

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Data centre disaggregation with Gen-Z and CXL

Part 1: CXL and Gen-Z

• The Gen-Z and Compute Express Link (CXL) protocols have been shown working in unison to implement a disaggregated processor and memory system at the recent Supercomputing 21 show.

• The Gen-Z Consortium’s assets are being subsumed within the CXL Consortium. CXL will become the sole industry standard moving forward.

• Microsoft and Meta are two data centre operators backing CXL.

Pity Hiren Patel, tasked with explaining the Gen-Z and CXL networking demonstration operating across several booths at the Supercomputing 21 (SC21) show held in St. Louis, Missouri in November.

Hiren Patel

Not only was Patel wearing a sanitary mask while describing the demo but he had to battle to be heard above cooling fans so loud, you could still be at St. Louis Lambert International Airport.

Gen-Z and CXL are key protocols supporting memory and server disaggregation in the data centre.

The SC21 demo showed Gen-Z and CXL linking compute nodes to remote ‘media boxes’ filled with memory in a distributed multi-node network (see diagram, bottom).

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Books read in 2021: Part 2

In Part II, two more industry figures pick their reads of the year: Sara Gabba of II-VI and Ciena’s Joe Marsella.

Sara Gabba, Strategic Marketing, II-VI

I’ve always read a lot. I cannot fall asleep without the sweet or the exciting company of a good book!

In the last year, I’ve spent many evenings reading fairy tales to my young daughter and, on top of the traditional ones from Andersen or the Grimm brothers, I’ve surprisingly discovered that she really likes the Greek myths (in an adaptation for children), which are the archetypes of most of the ‘modern’ tales. Love, mystery, jealousy, fear, talent, heroism: all the instincts and passions of humankind are there and able to capture every reader.

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Marvell's 50G PAM-4 DSP for 5G optical fronthaul

• Marvell has announced the first 50-gigabit 4-level pulse-amplitude modulation (PAM-4) physical layer (PHY) for 5G fronthaul.

• The chip completes Marvell’s comprehensive portfolio for 5G radio access network (RAN) and x-haul (fronthaul, midhaul and backhaul).

Marvell's wireless portfolio of ICs. Source: Marvell.

Marvell has announced what it claims is an industry-first: a 50-gigabit PHY for the 5G fronthaul market.

Dubbed the AtlasOne, the PAM-4 PHY chip also integrates the laser driver. Marvell claims this is another first: implementing the directly modulated laser (DML) driver in CMOS.

“The common thinking in the industry has been that you couldn’t do a DML driver in CMOS due to the current requirements,” says Matt Bolig, director, product marketing, optical connectivity at Marvell. “What we have shown is that we can build that into CMOS.”

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Books read in 2021: Part 1

Each year Gazettabyte asks industry figures to pick their reads of the year. Paul Brooks and Maxim Kuschnerov kick off this year's recommended reads. 

Dr. Paul Brooks, Optical Transport Director, VIAVI Solutions

Having spent a very happy time serving in the Royal Navy, I am always reading about all things connected with its history.

As a young midshipman, I managed to sleep through many of the history lessons at BRNC Dartmouth so I am using my spare time to catch up on the lessons I missed all those years ago.

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Acacia's single-wavelength terabit coherent module

• Acacia has developed a 140-gigabaud, 1.2-terabit coherent module

• The module, using 16-ary quadrature amplitude modulation (16-QAM), can deliver an 800-gigabit wavelength over 90 per cent of the links of a North American operator.  

Acacia Communications, now part of Cisco, has announced the first 1.2-terabit single-wavelength coherent pluggable transceiver.

Tom Williams

And the first vendor, ZTE, has already showcased a prototype using Acacia’s single-carrier 1.2 terabit-per-second (Tbps) design.

The coherent module operates at a symbol rate of up to 140 gigabaud (GBd) using silicon photonics technology. Until now, indium phosphide has always been the material at the forefront of each symbol rate hike.

The module uses Acacia’s latest Jannu coherent digital signal processor (DSP), implemented in 5nm CMOS. The coherent transceiver also uses a custom form-factor pluggable dubbed the Coherent Interconnect Module 8 (CIM-8).

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