How to shepherd a company’s technologies for growth

CTO interviews part 3: Dr Julie Eng

• Eng is four months into her new role as CTO of Coherent.
• Previously, she headed Finisar’s transceiver business and then the 3D sensing business, first at Finisar and then at II-VI. II-VI changed its name to Coherent in September 2022
• “CTO is one of these roles that has no universal definition,” says Eng

Dr Julie Eng

Julie Eng loved her previous role.

She had been heading II-VI’s (now Coherent’s) 3D sensing unit after being VP of engineering at Finisar’s transceiver business. II-VI bought Finisar in 2019.

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Microchip expands the choice of 1.6-terabit Ethernet PHYs

Microchip Technology has enlarged its portfolio of 1.6-terabit physical layer (PHY) Ethernet chips targeting next-generation switch and router line cards.

Stephen Docking

In 2021, Microchip announced its PM6200 Meta-DX2L (‘L’ standing for light), its first 1.6-terabit Meta-DX2 PHY that uses 112-gigabit PAM-4 (4-level pulse-amplitude modulation) serialiser/ deserialisers (series).

Microchip has now added four more 1.6-terabit Ethernet PHYs dubbed Meta-DX2+.

Like the Meta-DX2L, the PHYs are implemented using a 6nm CMOS process while the ‘plus’ signifies added features.

The Meta-DX2L is used for such tasks as retiming, for a signal sent across the system’s backplane, for example, and has a ‘gearbox’ feature that translates between 28, 56 and 112-gigabit data rates.

With the Meta-DX2+ PHYs, Microchip has added port aggregation and security hardware.

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Microchip’s compact, low-power 1.6-terabit PHY

Microchip Technology’s latest physical layer (PHY) chip has been developed for next-generation line cards.

The PM6200 Meta-DX2L (the ‘L’ is for light) 1.6-terabit chip is implemented using TSMC's 6nm CMOS process. It is Microchip’s first PHY to use 112-gigabit PAM-4 (4-level pulse-amplitude modulation) serialiser/ deserialisers (serdes) interfaces.

Stephen Docking

Microchip’s existing 16nm CMOS Meta-DX1 PHY devices are rated at 1.2 terabits and use 56-gigabit PAM-4 serdes.

System vendors developing line cards that double the capacity of their switch, router or transport systems are being challenged by space and power constraints, says Microchip. To this aim, the company has streamlined the Meta-DX2L to create a compact, lower-power chip.

“One of the things we have focussed on is the overall footprint of our [IC] design to ensure that people can realise their cards as they go to the 112-gigabit PAM-4 generation,” says Stephen Docking, manager, product marketing, communications business unit at Microchip.

The company says the resulting package measures 23x30mm and reduces the power per port by 35 per cent compared to the Meta-DX1.

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COBO issues industry’s first on-board optics specification

• COBO modules supports 400-gigabit and 800-gigabit data rates   
• Two electrical interfaces have been specified: 8 and 16 lanes of 50-gigabit PAM-4 signals. 
• There are three module classes to support designs ranging from client-slide multi-mode to line-side coherent optics. 
• COBO on-board optics will be able to support 800 gigabits and 1.6 terabits once 100-gigabit PAM-4 electrical signals are specified. 

Source: COBO

Interoperable on-board optics has moved a step closer with the publication of the industry’s first specification by the Consortium for On-Board Optics (COBO).

COBO has specified modules capable of 400-gigabits and 800-gigabits rates. The designs will also support 800-gigabit and 1.6-terabit rates with the advent of 100-gigabit single-lane electrical signals. 

“Four hundred gigabits can be solved using pluggable optics,” says Brad Booth, chair of COBO and principal network architect for Microsoft’s Azure Infrastructure. “But if I have to solve 1.6 terabits in a module, there is nothing out there but COBO, and we are ready.”

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