Microchip expands the choice of 1.6-terabit Ethernet PHYs

Microchip Technology has enlarged its portfolio of 1.6-terabit physical layer (PHY) Ethernet chips targeting next-generation switch and router line cards.

Stephen Docking

In 2021, Microchip announced its PM6200 Meta-DX2L (‘L’ standing for light), its first 1.6-terabit Meta-DX2 PHY that uses 112-gigabit PAM-4 (4-level pulse-amplitude modulation) serialiser/ deserialisers (series).

Microchip has now added four more 1.6-terabit Ethernet PHYs dubbed Meta-DX2+.

Like the Meta-DX2L, the PHYs are implemented using a 6nm CMOS process while the ‘plus’ signifies added features.

The Meta-DX2L is used for such tasks as retiming, for a signal sent across the system’s backplane, for example, and has a ‘gearbox’ feature that translates between 28, 56 and 112-gigabit data rates.

With the Meta-DX2+ PHYs, Microchip has added port aggregation and security hardware.

Click to read more ...

Microchip’s compact, low-power 1.6-terabit PHY

Microchip Technology’s latest physical layer (PHY) chip has been developed for next-generation line cards.

The PM6200 Meta-DX2L (the ‘L’ is for light) 1.6-terabit chip is implemented using TSMC's 6nm CMOS process. It is Microchip’s first PHY to use 112-gigabit PAM-4 (4-level pulse-amplitude modulation) serialiser/ deserialisers (serdes) interfaces.

Stephen Docking

Microchip’s existing 16nm CMOS Meta-DX1 PHY devices are rated at 1.2 terabits and use 56-gigabit PAM-4 serdes.

System vendors developing line cards that double the capacity of their switch, router or transport systems are being challenged by space and power constraints, says Microchip. To this aim, the company has streamlined the Meta-DX2L to create a compact, lower-power chip.

“One of the things we have focussed on is the overall footprint of our [IC] design to ensure that people can realise their cards as they go to the 112-gigabit PAM-4 generation,” says Stephen Docking, manager, product marketing, communications business unit at Microchip.

The company says the resulting package measures 23x30mm and reduces the power per port by 35 per cent compared to the Meta-DX1.

Click to read more ...

Microchip launches the first terabit physical layer device

Microchip Technology has unveiled a family of physical layer (PHY) Ethernet devices with a capacity of 1.2 terabits.

The Meta-DX1 PHY family comprises three devices that support three 400 Gigabit Ethernet (GbE) channels, a dozen 100GbE channels or 24, 10GbE channels. 

“We are not aware of any PHY in the industry that supports more than one terabit of traffic,” says Stephen Docking, manager, product marketing at the communications business unit of Microchip. 

The company is also claiming another industry first in offering a PHY that supports the Open Internetworking Forum’s (OIF) Flexible Ethernet (FlexE) standard. 

Click to read more ...