Acacia targets access networks with coherent QSFP-DD

• Acacia Communications has announced a 100-gigabit coherent QSFP-DD pluggable module.
• The module is the first of several for aggregation in the access network.

The second article addressing what next for coherent

Part 2: 100-gigabit coherent QSFP-DD

Acacia Communications has revisited 100-gigabit coherent but this time for access rather than metro networks.

Acacia’s metro 100-gigabit coherent pluggable product, a CFP, was launched in 2014. The pluggable has a reach from 80km to 1,200km and consumes 24-26W.

Tom Williams

The latest coherent module is the first QSFP-DD to support a speed lower than the 400-gigabit 400ZR and ZR+ applications that have spurred the coherent pluggable market. 

The launching of a 100-gigabit coherent QSFP-DD reflects a growing need to aggregate 10 Gigabit Ethernet (GbE) links at the network edge as 5G and fibre are deployed.

“The 10GbE links in all the different types of access networks highlight a need for a cost-effective way to do this aggregation,” says Tom Williams, vice president of marketing at Acacia.

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Is traffic aggregation the next role for coherent?

Ciena and Infinera have each demonstrated the transmission of 800-gigabit wavelengths over near-1,000km distances, continuing coherent's marked progress. But what next for coherent now that high-end optical transmission is approaching the theoretical limit? Can coherent compete over shorter spans and will it find new uses?

The first of several articles addressing what next for coherent.

Part 1: XR Optics

“I’m going to be a bit of a historian here,” says Dave Welch, when asked about the future of coherent.

Interest in coherent started with the idea of using electronics rather than optics to tackle dispersion in fibre. Using electronics for dispersion compensation made optical link engineering simpler.

Dave Welch

Coherent then evolved as a way to improve spectral efficiency and reduce the cost of sending traffic, measured in gigabit-per-dollar.

“By moving up the QAM (quadrature amplitude modulation) scale, you got both these benefits,” says Welch, the chief innovation officer at Infinera.

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Open Eye MSA gets webscale attention

Microsoft has trialled optical modules that use signalling technology developed by the Open Eye Consortium.

The webscale player says optical modules using the Open Eye’s analogue 4-level pulse-amplitude modulation (PAM-4) technology consume less power than modules with a PAM-4 digital signal processor (DSP).

“Open Eye has shown us at least an ability that we can do better on power,” says Brad Booth, director, next cloud system architecture, Azure hardware systems and infrastructure at Microsoft, during an Open Eye webinar.

Brad BoothOptical module power consumption is a key element of the total power budget of data centres that can have as many as 100,000 servers and 50,000 switches.

“You want to avoid running past your limit because then you have to build another data centre,” says Booth.

But challenges remain before Open Eye becomes a mainstream technology, says Dale Murray, principal analyst at market research firm, LightCounting.

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Silicon photonics' second wave

• “I believe the field of silicon photonics is at a pivotal point of change and acceleration.” 

• Professor Roel Baets, the winner of the 2020 John Tyndall Award, talks about what motivates his research and his interests.

Two concentric circles drawn in chalk are shown on-screen. So Professor Roel Baets open his plenary talk at the European Conference on Integrated Optics (ECIO) 2020, asking the online audience what is being shown.

Professor Roel Baets

Suggestions come flooding in: the cross-section of an optical fibre, a silicon wafer, a ring resonator optical component and - the correct answer - a doughnut.

The image is from the front cover of Doughnut Economics: Seven Ways to Think Like a 21st-Century Economist by Kate Raworth, a UK professor of economics.

The author discusses how continual economic growth is out of kilter with the planet’s well-being and details alternative approaches. The “doughnut” represents a sweet-spot region ensuring sustainable growth.

Baets applied the book’s thinking to his plenary talk on the topic of silicon photonics research.

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Silicon photonics webinar

Daryl Inniss and I assess how the technology and marketplace has changed since we published our silicon photonics book at the end of 2016. Click here to view the webinar. Ours is the first of a series of webinars that COBO, the Consortium of On-Board Optics, is hosting.

And here is a copy of the slides, click here.

The IEEE gears up for the next Ethernet standard

Completing an Ethernet specification takes years of effort. Just ask John D’Ambrosia of Futurewei who has spent the last 15 years chairing various IEEE Ethernet standards.

John D'Ambrosia

He oversaw the standardisation of 40/100 Gigabit Ethernet (GbE) and 200/400GbE and he is now chairing two IEEE Task Forces standards addressing 100 and 400 coherent Ethernet.

He is also the Chair of the group looking at new Ethernet applications (NEA) or to give it its full title, the IEEE 802.3 Industry Connections NEA Ad Hoc group.

D’Ambrosia is driving the development of the ‘Beyond 400 Gigabit’ Call-for-Interest work of the NEA group that will define the next Ethernet standard.

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Xilinx’s Versal Premium ready for the 800-gigabit era

When Xilinx was created in 1984, the founders banked on programmable logic becoming ever more attractive due to Moore’s law.

Making logic programmable requires extra transistors so Xilinx needed them to become cheaper and more plentiful, something Moore’s law has delivered, like clockwork, over decades.

Kirk SabanSince then, Xilinx’s field-programmable gate array (FPGA) devices have advanced considerably.

Indeed, Xilinx’s latest programmable logic family, the Versal Premium, is no longer referred to as an FPGA but as an adaptive compute accelerator platform (ACAP).

The Versal Premium series of chips, to be implemented using TSMC’s 7nm CMOS process, was unveiled for the OFC 2020 show. The Premium series will have seven chips with the largest, the VP1802, having 50 billion transistors.

First devices will ship in the second half of 2021.

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