Acacia bets on silicon as coherent enters its next phase

Gazettabyte interviewed Acacia Communications’ president and CEO, Murugesan ‘Raj’ Shanmugaraj, as the coherent technology company celebrates its 10th anniversary.

 

Raj Shanmugaraj

Raj Shanmugaraj

 

Acacia Communications has come a long way since Raj Shanmugaraj (pictured) first joined the company as CEO in early 2010. “It was just a few conference rooms and we didn't have enough chairs,” he says.

The company has since become a major optical coherent player with revenues of $340 million in 2018; revenues that would have been higher but for the four-month trade ban imposed by the US on Chinese equipment maker ZTE, an Acacia customer.

And as the market for coherent technology continues to grow, Acacia and other players are preparing for new opportunities. 

“We are still in the early stages of the disruption," says Shanmugaraj. “You will see higher performance [coherent systems] in some parts of the network but there is going to be growth as coherent moves closer to the network edge.” 

Here, lower power, flexibility and more integrated coherent solutions will be needed as the technology moves inside the data centre and closer to the network edge with the advent of 5G, higher-speed access and the Internet of Things (IoT). 

Competitive landscape

Shanmugaraj prefers to focus on Acacia’s own strengths and products when asked about the growing competition in the coherent marketplace. However, recent developments present challenges for the company.

Systems vendors such as Huawei and Ciena are becoming more vertically integrated, developing not only their own coherent digital signal processor (DSP) ASICs but also optics. Ciena has also made its WaveLogic Ai DSP available to optical module makers Lumentum and NeoPhotonics and will sell its own optical modules using its latest WaveLogic 5 coherent silicon.

 

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You will see higher performance [coherent systems] in some parts of the network but there is going to be growth as coherent moves closer to the network edge 

 

New coherent digital signal processor (DSP) players are also expected to enter the marketplace alongside established competitors, NEL and Inphi. The entrance of new players developing coherent DSPs is motivated by the unit volumes promised by 400ZR, the emerging 80km data centre interconnect interface standard.

“We are proponents of the fact that the merchant market will continue to grow, driven by interoperability and standardisation,” says Shanmugaraj. Such growth will lead to multiple markets where coherent technology will play. “There are going to be a few winners, not just one or two,” he says.

Acacia’s revenues were hit in 2018 following the US Department of Commerce’s enforced trade ban imposed on ZTE. However, the company recorded a strong fourth quarter posting revenues of $107 million, up almost a quarter on the revenues a year earlier. This followed strong ZTE orders after the ban was revoked.

Shanmugaraj says diversification has always been a priority for the company, independent of the trade issues between the US and China. The company has also been working to diversify its Chinese customer base. “So we are well positioned as these trade issues get resolved,” he says.

Origins

Acacia was established in mid-2009 by a core team from Mintera, a sub-system supplier that provided 40-gigabit DPSK line cards to network equipment suppliers. But Mintera folded and was eventually sold to Oclaro in July 2010.

Before joining Acacia, Shanmugaraj was at systems vendor Alcatel-Lucent where he learned two lessons.

One is that the long-term success of a company is based on technology leadership. “You want to be driven by technology or you fall behind your competitors,” he says. The second lesson was that the largest systems companies build products internally before an ecosystem becomes established, after which they buy from merchant suppliers.

This matched the vision of Acacia’s founders that sought to exploit their optical expertise gained at Mintera to become a leading merchant supplier of coherent transmission technology.

Stealth years

Acacia remained in secrecy for nearly half its existence, only revealing its technology and products in 2014 with the launch of the AC-100 CFP coherent pluggable module. The AC-100 is aimed at metro networks delivering a transmission reach of 80km to 1,200km. However, Acacia had already been selling 5x7-inch modules for 100-gigabit long-haul and ultra-long-haul applications as well as a 40-gigabit ultra-long-haul module.

“In the early years, there were just a few companies working on coherent,” says Shanmugaraj. “We had to be careful in terms of what products we were developing and what customers we were going after.”

Shanmugaraj says Acacia secured multi-million dollar commitments from customers even before it had a product. “It was the expertise of the founding team as well as the product concepts they were proposing that got them the commitments,” he says.

The backing enabled the company to manage with only $53 million of venture funding prior to its successful initial public offering in 2016.

“This was a pretty significant feat,” says Shanmugaraj. “Hardware start-ups, whether semiconductor or systems companies, use significantly more cash; these are expensive technologies to get off the ground.”

Shanmugaraj describes the early years as intense, with staff working between 60 and 70 hours a week.The then start-up had to be prudent with funding, not growing too quickly yet having sufficient resources to meet orders from systems customers that had their own orders to fulfil.

Coherent technologies

Acacia’s founders chose silicon for its coherent solutions, to replace ‘exotic materials’ such as indium phosphide and lithium niobate used in traditional optical transmission systems. 

The company backed silicon photonics for the coherent optics, an industry trailblazing decision. To this aim, Acacia recruited Chris Doerr, the renowned optical integration specialist and Bell Labs Fellow

The company also decided to develop its own coherent DSPs. By developing the optics and the DSP, Acacia could use a co-design approach when designing the hardware, trading off the performance of the optics and the signal processing to achieve an optimal design.

Shanmugaraj explains that the company chose a silicon-based approach to exploit the huge investment made by the semiconductor industry in chips and their packaging. Basing the components on silicon would not only simplify high-speed networks, he says, but it would also lower their power consumption and enable products to be made more quickly and cheaply.

“The beauty of silicon photonics is that it can be placed right next to a heat source, in this case, the high-power coherent DSP ASIC that generates a lot of heat,” says Shanmugaraj. “This allows for smaller form-factor designs.” In contrast, indium phosphide-based optics need to be temperature controlled when placed next to a hot chip, he says.

“Five or six years ago, people were challenging whether silicon photonics was even going to work at 100 and 200 gigabits,” says Shanmugaraj. Acacia has now used silicon photonics in all its products, including its latest high-end 1.2 terabits AC1200 coherent module.

Shanmugaraj sees Acacia's portfolio of coherent products as the company's biggest achievement: "You see start-ups that come out with one product that is a bestseller but we have continued to innovate and today we have a broad portfolio."   

AC1200

The AC1200 module supports two optical wavelengths, each capable of supporting 100 to 600-gigabit transmissions in increments of 50 gigabits.

The AC1200 can be used for data centre interconnect links through to long distance submarine links. Acacia recently demonstrated the AC1200 transmitting a 400-gigabit signal over a 6,600km submarine cable

“We are seeing strong interest in our AC1200 from network operators and expect our equipment customers to begin deployments this quarter,” says Shanmugaraj.

There are several reasons why network operators are choosing to deploy the AC1200, he says: “High capacity is important in data centre interconnect edge applications where we expect hyperscale operators may use the AC1200 in its full 1.2-terabit mode, but these applications are also sensitive to cost, power and density.” 

The AC1200 also provides higher capacity in a smaller footprint than the 5x7-inch form factors currently available, he says, while for longer-reach applications, the AC1200 offers a combination of performance and flexibility that is setting the pace for the competition.

The data centre interconnect market represents a good opportunity for coherent interconnect suppliers because the operators drive and deploy technology at pace, says Shanmugaraj. Hyperscalers are continually looking to add more capacity in the same size and power constraints that exist today. Accordingly, this has been a priority development area for Acacia.

To increase capacity, companies have boosted the symbol rate from 32 gigabaud to 64 gigabaud while systems vendors Ciena and Infinera have recently detailed upcoming systems that support 800-gigabit wavelengths that use a symbol rate approaching 100 gigabaud.

The AC1200, which is due in systems in the coming quarter, demonstrates silicon photonics based modulation operating at up to 70 gigabaud while first indium-phosphide 800-gigabit per wavelength systems are due by the year-end.

“We don’t really see silicon photonics lagging behind indium phosphide,” says Shanmugaraj. “We think there is a path to even higher baud rates with silicon photonics, and 128 gigabaud is the next logical step up because it would double the data rate without needing to increase the modulation order.”

Higher modulation orders are also possible but the benefits must be weighed against increased complexity, he says.  

400-gigabit coherent pluggables

Shanmugaraj says that the 400ZR pluggable module standard continues the trend to reduce the size and power consumption of optical transport systems in the data centre.

 

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You want to be driven by technology or you fall behind your competitors

 

The current generation of data centre interconnect platforms, ranging from a 1 rack unit pizza box to a several rack-unit-sized chassis, were developed to be more compact than conventional optical transport platforms.

Now, with the advent of 400ZR that fits into a client-side QSFP-DD or OSFP module, data centre operators will be able to do away with such platforms for distances up to 80km by plugging the modules into the switch or router platforms and connecting them to open line systems.

“Costs come down because it [coherent] is getting down to the client-side form factors and that gives the hyperscalers more faceplate density,” says Shanmugaraj. “The hyperscalers also gain multi-vendor interoperability [with 400ZR] which is important as they want standardisation.”

Shanmugaraj admits that with the advent of 400ZR will bring greater competition. But he points out that the 400ZR is a complicated product to built that will challenge companies. Those players that have both the optics and a low-power DSP will have an advantage. “As long as it opens up the market wider, it is good for Acacia as it is in our control how we can win in the market,” says Shanmugaraj.

The industry expectation is that the 400ZR will start to be deployed in the second half of 2020.

There is also industry talk about 400ZR+, an interface that will be able to go beyond 80km that will require more advanced dispersion compensation and forward error correction schemes. 

Shanmugaraj says it will be the same DSP ASIC that will support both the 400ZR and 400ZR+. However, a 400ZR+ interface will consume more power and so will likely require a larger module form factor than the ZR.

Meanwhile, the 400-gigabit CFP2-DCO pluggable for metro networks is built along the same lines as the 400ZR, says Shanmugaraj.

“Here you have applications like the Open ROADM MSA where network operators are trying to drive the same interoperability and not be stuck with one vendor,” he says. “This is driving the 400-gigabit evolution in the metro network for some of the largest telcos.”

There is also the open networking packet-optical opportunity, white-box platforms such as the Voyager and Cassini being developed by the Telecom Infra Project (TIP). Shanmugaraj says such white boxes rely on software solutions that are a work-in-progress and that much work is still to be done.

“The first generation showed that there is more work required to standardise the software and how that can be used by the hyperscalers,” he says. “It is an opportunity but we view it as more of a longer-term one.”

Emerging opportunities

The markets that are growing today are the metro, long haul, sub-sea and data centre interconnect, says Shanmugaraj.

The coherent applications that are emerging will result in products within the data centre as well as for 5G, access, the Internet of Things (IoT) and even autonomous vehicles.

Ultimately, what will lead to coherent being adopted within the data centre is the speed of the interfaces. “As you go to higher speeds, direct detection technology gets constrained [due to dispersion and other impairments],” says Shanmugaraj. 

But for this to happen certain conditions will need to be met: the speed of interfaces on switches will need to increase, not just to 400 gigabits but 800 gigabits and greater.

“Looking to higher data rates beyond 400 gigabits, it gets more challenging for direct detect to achieve the necessary link budgets cost-effectively,” says Shanmugaraj. “It may be necessary to move from four-lane solutions to eight lanes in order to support the desired reaches. At the same time, we are working to make coherent more cost-effective for these applications.” 

The other two conditions are the challenge of what form factors the coherent technology be squeezed into, andcost. Coherent optics is more expensive but its cost is driven by such factors as volumes, the level of automation that can be used to make the module, and the yield.

“There could be inflextion points where coherent becomes cost-competitive for some applications in the data centre,” says Shanmugaraj. 

Companies will continue to innovate in both direct detect and coherent technologies and the market will determine the transition points. “But we do believe that coherent can be adopted inside data centres in the future,” he says.

In turn, metro and long-haul networks are already being upgraded in anticipation of 5G and the access requirements. “4G networks have a lot of 1-gigabit and 10-gigabit links but 5G has an order of magnitude higher throughput requirement,” says Shanmugaraj. 

That means more capacity is needed for backhaul and that will lead to a proliferation of low-cost 100-gigabit coherent. A similar story is unfolding in access with the likes of the cable operators moving fibre closer to the network edge. This too will need low-cost 100-gigabit coherent interfaces.

IoT is a longer term opportunity and will be dependent on dense deployments of devices before the traffic will require sufficient aggregation to justify coherent.

“I don’t know if your refrigerator will have a coherent interface,” concludes Shanmugaraj. “But as you aggregated these [devices] into aggregation points, that becomes a driver for coherent at the edge.”


Creating a long-term view for the semiconductor industry

The semiconductor industry is set for considerable change over the next 15 years.

“We are at an inflection point in the history of the [chip] industry,” says Thomas Conte, an IEEE Fellow. “It will be very different and very diverse; there won’t be one semiconductor industry.” 

 

 

Conte (pictured) is co-chair of the IEEE Rebooting Computing initiative that is sponsoring the International Roadmap of Devices and Systems (IRDS) programme (See The emergence of the IRDS, below). The IRDS is defining technology roadmaps over a 15-year horizon and in November will publish its first that spans nine focus areas. 

The focus of the IRDS on systems and devices and the broadening of technologies being considered is a consequence of the changing dynamics of the chip industry.

Conte stresses that it is not so much the ending of Moore’s Law that is causing the change as the ending of CMOS. Transistors will still continue to shrink even though it is becoming harder and costlier to achieve but the scaling benefits that for decades delivered a constant power density for chips with each new CMOS process node ended a decade ago.

“Back in the day it was pretty easy to plot it [the roadmap] because the technology was rather static in what we wanted to achieve,” says Conte. That ‘cushy ride’ that CMOS has delivered is ending. “The question now is: Are there other technologies we should be investing in that help applications move forward?” says Conte.

 

Focus groups

The IRDS has set up nine focus groups and in March published the first white papers from the teams. 

The most complete white paper is from the More Moore focus group which looks at how new generations of smaller transistor features will be achieved. “It is clear that for the next 10 to 15 years we still have a lot of CMOS nodes left,” says Conte. “We still have to track what happens to CMOS.”

Conte says it is becoming clearer that ICs, in general, are going to follow the course of flash memory and be constructed as 3D monolithic designs. “We are just beginning to understand how to do this," says Conte.

"This does not mean we are going to get transistors that make computing faster without doing something different,” he says. This explains the work of the Beyond CMOS (Emerging Research Devices) focus team that is looking at alternative non-CMOS technologies to advance systems performance.

 

It is clear that for the next 10 to 15 years we still have a lot of CMOS nodes left

 

A third IRDS focus group is Outside System Connectivity which includes interface technologies such as photonic interconnect needed for future systems. “Outside System Interconnect is an important focus group and it is also our interface to the IEEE 5G roadmap team,” he says.

Conte also highlights two other IRDS focus teams: System and Architecture, and Applications Benchmarking. “These two focus teams are really important as to what the IRDS is all about,” says Conte.

The System and Architecture group has identified four systems views that it will focus on: the data centre, mobile handsets and tablets, edge devices for the Internet of Things, and control systems for the cyber-physical world such as automation, robotics and automotive systems.  

The Application Benchmarking focus group is tasked with predicting key applications, quantifying how their performance is evolving and identifying roadblocks that could hinder their progress. Feature recognition, an important machine learning task, is one such example.

The IRDS is also continuing the working format established by the ITRS whereby every odd year a new 15-year roadmap is published while updates are published every even year.

 

Roadmapping

Three communities contribute to the development of the IRDS roadmap: industry, government and academia.

Industry is more concerned with solving their immediate problems and do not have the time or resources to investigate something that might or might not work in 15 years’ time, says Conte. Academia, in contrast, is more interested in addressing challenging problems over a longer term, 15-year horizon. Government national labs in the US and Europe’s imec sit somewhere in between and try to come up with mid-range solutions. “It is an interesting tension and it seems to work,” says Conte.  

Contributors to the IRDS are from the US, Europe, Japan, South Korea and Taiwan but not China which is putting huge effort to be self-sufficient in semiconductors.

“We have not got participation for China yet,” says Conte. “It is not that we are against that, we just have not made the connections yet.” Conte believes China’s input would be very good for the roadmap effort. “They are being very aggressive and bright and they are more willing to take risks than the West,” he says. 

What will be deemed a success for the IRDS work?

“It is to come up with a good prediction that is 15 years out and identify what the roadblocks are to getting there.”  

 

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The emergence of the IRDS

The IRDS was established in 2016 by the IEEE after it took over the roadmap work of the International Technology Roadmap for Semiconductors (ITRS), an organisation sponsored by the five leading chip manufacturing regions in the world.

“The [work of the] ITRS was a bottoms-up roadmap, driven by the semiconductor industry,” says Conte. “It started with devices and didn't really go much higher.”

With the end of scaling, whereby the power density of chips remained constant with each new CMOS process node, the ITRS realised its long-established roadmap work needed a rethink which resulted in the establishment of ITRS 2.0. 

“The ITRS 2.0 was an attempt to do a top-down approach looking at the system level and working down to devices,” says Conte. It was well received by everyone but the sponsors, says Conte, which was not surprising given their bottoms-up focus. It resulted in the sponsors of the ITRS 2.0 such as the US Semiconductor Industry Association (SIA) pulling out and the IEEE stepping in.

“This is much closer to what we are trying to do with the Rebooting Computing so it makes sense this group comes into the IEEE band and we act as a sponsor,” says Conte.


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