Imec eyes silicon photonics to solve chip I/O bottleneck
In the second and final article, the issue of adding optical input-output (I/O) to ICs is discussed with a focus on the work of the Imec nanoelectronics R&D centre that is using silicon photonics for optical I/O.
Part 2: Optical I/O
Imec has demonstrated a compact low-power silicon-photonics transceiver operating at 40 gigabits per second (Gbps). The silicon photonics transceiver design also uses 14nm FinFET CMOS technology to implement the accompanying driver and receiver electronics.
Joris Van Campenhout“We wanted to develop an optical I/O technology that can interface to advanced CMOS technology,” says Joris Van Campenhout, director of the optical I/O R&D programme at Imec. “We want to directly stick our photonics device to that mainstream CMOS technology being used for advanced computing applications.”
Traditionally, the Belgium nanoelectronics R&D centre has focussed on scaling logic and memory but in 2010 it started an optical I/O research programme. “It was driven by the fact that we saw that electrical I/O doesn’t scale that well,” says Van Campenhout. Electrical interfaces have power, space and reach issues that get worse with each hike in transmission speed.
Imec is working with partner companies to research optical I/O. The players are not named but include semiconductor foundries, tool vendors, fabless chip companies and electronic design automation tools firms. The aim is to increase link capacity, bandwidth density - a measure of the link capacity that can be crammed in a given space - and reach using optical I/O. The research’s target is to achieve between a 10x to 100x in scaling.
The number of silicon photonics optical I/O circuits manufactured each year remains small, says Imec, several thousand to ten thousand semiconductor wafers at most. But Imec expects volumes to grow dramatically over the next five years as optical interconnects are used for ever shorter reaches, a few meters and eventually below one meter.
“That is why we are participating in this research, to put together building blocks to help in the technology pathfinding,” says Van Campenhout.
We wanted to develop an optical I/O technology that can interface to advanced CMOS technology
Silicon photonics transceiver
Imec has demonstrated a 1330nm optical transceiver operating at 40Gbps using non-return-to-zero signalling. The design uses hybrid integration to combine silicon photonics with 14nm FinFET CMOS electronics. The resulting transceiver occupies 0.025 mm2, the area across the combined silicon photonics and CMOS stack for a single transceiver channel. This equates to a bandwidth density of 1.6 terabit-per-second/mm2.
The silicon photonics and FinFET test chips each contain circuitry for eight transmit and eight receive channels. Combined, the transmitter path comprises a silicon photonics ring modulator and a FinFET differential driver while the receiver uses a germanium-based photo-detector and a first-stage FinFET trans-impedance amplifier (TIA).
The transceiver has an on-chip power consumption of 230 femtojoules-per-bit, although Van Campenhout stresses that this is a subset of the functionality needed for the complete link. “This number doesn’t include the off-chip laser power,” he says. “We still need to couple 13dBm - 20mW - of optical power in the silicon photonics chip to close the link budget.” Given the laser has an efficiency of 10 to 20 percent, that means another 100mW to 200mW of power.
That said, an equivalent speed electrical interface has an on-chip power consumption of some 2 picojoules-per-bit so the optical interface still has some margin to better the power efficiency of the equivalent electrical I/O. In turn, the optical I/O’s reach using single-mode fibre is several hundred meters, far greater than any electrical interface.
Imec is confident it can increase the optical interface’s speed to 56Gbps. The layout of the CMOS circuits can be improved to reduce internal parasitic capacitances while Imec has already improved the ring modulator design compared to the one used for the demonstrator.
“We believe that with a few design tweaks we can get to 56Gbps comfortably,” says Van Campenhout. “After that, to go faster will require new technology like PAM-4 rather than non-return-to-zero signalling.”
Imec has also tested four transmit channels using cascaded ring modulators on a common waveguide as part of work to add a wavelength-division multiplexing capability.
Transceiver packaging
The two devices - the silicon photonics die and the associated electronics - are combined using chip-stacking technology.
Both devices use micro-bumps with a 50-micron pitch with the FinFET die flip-chipped onto the silicon photonics die. The combined CMOS and silicon photonics assembly is glued on a test board and wire-bonded, while the v-groove fibre arrays are attached using active alignment. The fibre-to-chip coupling loss, at 4.5dB in the demonstration, remains high but the researchers say this can be reduced, having achieved 2dB coupling losses in separate test chips.
Source: Imec.
Imec is also investigating using through-silicon vias (TSV) technology and a silicon photonics interposer in order to replace the wire-bonding. TSVs deliver better power and ground signals to the two dies and enable high-speed electrical I/O between the transceiver and the ASIC such as a switch chip. The optics and ASIC could be co-packaged or the transceiver used in an on-board optics design next to the chip.
“We have already shown the co-integration of TSVs with our own silicon photonics platform but we are not yet showing the integration with the CMOS die,” says Van Campenhout. “Something we are working on.”
Co-packaging the optics with silicon will come at a premium cost
Applications
The first ICs to adopt optical I/O will be used in the data centre and for high-performance computing. The latest data centre switch ICs, with a capacity of 12.8 terabits, are implemented using 16nm CMOS. Moving to a 7nm CMOS process node will enable capacities of 51.2 terabits. “These are the systems where the bandwidth density challenge is the largest,” says Van Campenhout.
But significant challenges must be overcome before this happens, he says: “I think we all agree that bringing optics deeply integrated into such a product is not a trivial thing.”
Co-packaging the optics with silicon will come at a premium cost. There are also reliability issues to be resolved and greater standardisation across the industry will be needed as to how the packaging should be done.
Van Campenhout expects this will only happen in the next four to five years, once the traffic-handling capacity of switch chips doubles and doubles again.
Imec has seen growing industry interest in optical I/O in the last two years. “We have a lot of active interactions so interest is accelerating now,” says Van Campenhout.
Ciena brings data analytics to optical networking
- Ciena's WaveLogic Ai coherent DSP-ASIC makes real-time measurements, enabling operators to analyse and adapt their networks.
- The DSP-ASIC supports 100-gigabit to 400-gigabit wavelengths in 50-gigabit increments.
- The WaveLogic Ai will be used in Ciena’s systems from 2Q 2017.
Ciena has unveiled its latest generation coherent DSP-ASIC. The device, dubbed WaveLogic Ai, follows Ciena’s WaveLogic 3 family of coherent chips which was first announced in 2012. The Ai naming scheme reflects the company's belief that its latest chipset represents a significant advancement in coherent DSP-ASIC functionality.
Helen XenosThe WaveLogic Ai is Ciena's first DSP-ASIC to support two baud rates, 35 gigabaud for fixed-grid optical networks and 56 gigabaud for flexible-grid ones. The design also uses advanced modulation schemes to optimise the data transmission over a given link.
Perhaps the most significant development, however, is the real-time network monitoring offered by the coherent DSP-ASIC. The data will allow operators to fine-tune transmissions to adapt to changing networking conditions.
“We do believe we are taking that first step towards a more automated network and even laying the foundation for the vision of a self-driving network,” says Helen Xenos, director, portfolio solutions marketing at Ciena.
All those assumptions of the past [based on static traffic] aren't holding true anymore
Network Analytics
Conservative margins are used when designing links due to a lack of accurate data regarding the optical network's status. This curtails the transmission capacity that can be sent since a relatively large link margin is used. In turn, cloud services and new applications mean networks are being exercised in increasingly dynamic ways. “The business environment has changed a little bit,” says Joe Cumello, vice president, portfolio marketing at Ciena. “All those assumptions of the past [based on static traffic] aren't holding true anymore.”
Ciena is being asked by more and more operators to provide information as to what is happening within their networks. Operators want real-time data that they can feed to analytics software to make network optimisation decisions. "Imagine a network where, instead of those rigid assumptions in place, run on manual spreadsheets, the network is making decisions on its own," says Cumello.
WaveLogic Ai performs real-time analysis, making available network measurements data every 10ms. The data can be fed through application programming interfaces to analytics software whose output is used by operators to adapt their networks.
Joe Cumello
The network parameters collected include the transmitter and receiver optical power, polarisation channel and chromatic dispersion conditions, error rates and transmission latency. In addition, the DSP-ASIC separates the linear and non-linear noise components of the signal-to-noise ratio. An operator will thus see what the network margin is and allow links to operate more closely to the limit, improving transmissions by exploiting the WaveLogic Ai's 50-gigabit transmission increments.
"Maybe there are only a few wavelengths in the network such that the capacity can be cranked up to 300 gigabits. But as more and more wavelengths are added, if you have the tools, you can tell the operator to adjust,” says Xenos. “This helps them get to the next level; something that has not been available before.”
WaveLogic Ai
The WaveLogic Ai's lower baud rate - 35 gigabaud - is a common symbol rate used by optical transmission systems today. The baud rate is suited to existing fixed-grid networks based on 50GHz-wide channels. At 35 gigabaud, the WaveLogic Ai supports data rates from 100 to 250 gigabits-per-second (Gbps).
The second, higher 56 gigabaud rate enables 400Gbps single-wavelength transmissions and supports data rates of 100 to 400Gbps in increments of 50Gbps.
Using 35 gigabaud and polarisation multiplexing, 16-ary quadrature amplitude modulation (PM-16QAM), a 200-gigabit wavelength has a reach is 1,000km.
With 35-gigabaud and 16-QAM, effectively 8 bits per symbol are sent.
In contrast, 5 bits per symbol are used with the faster 56 gigabaud symbol rate. Here, a more complex modulation scheme is used based on multi-dimensional coding. Multi-dimensional formats add additional dimensions to the four commonly used based on real and imaginary signal components and the two polarisations of light. The higher dimension formats may use more than one time slot, or sub-carriers in the frequency domain, or even use both techniques.
For the WaveLogic Ai, the 200-gigabit wavelength at 56 gigabaud achieves a reach of 3,000km, a threefold improvement compared to using a 35 gigabaud symbol rate. The additional reach occurs because fewer constellation points are required at 56 gigabaud compared to 16-QAM at 35 gigabaud, resulting in a greater Euclidean distance between the constellation points. "That means there is a higher signal-to-noise ratio and you can go a farther distance," says Xenos. "The way of getting to these different types of constellations is using a higher complexity modulation and multi-dimensional coding."
We do believe we are taking that first step towards a more automated network and even laying the foundation for the vision of a self-driving network
The increasingly sophisticated schemes used at 56 gigabaud also marks a new development whereby Ciena no longer spells out the particular modulation scheme used for a given optical channel rate. At 56 gigabaud, the symbol rate varies between 4 and 10 bits per symbol, says Ciena.
The optical channel widths at 56 gigabaud are wider than the fixed grid 50GHz. "Any time you go over 35 gigabaud, you will not fit [a wavelength] in a 50GHz band," says Xenos.
The particular channel width at 56 gigabaud depends on whether a super-channel is being sent or a mesh architecture is used whereby channels of differing widths are added and dropped at network nodes. Since wavelengths making up a super-channel go to a single destination, the channels can be packed more closely, with each channel occupying 60GHz. For the mesh architecture, guard bands are required either side of the wavelength such that a 75GHz optical channel width is used.
The WaveLogic Ai enables submarine links of 14,000km at 100Gbps, 3,000km links at 200Gbps (as detailed), 1,000km at 300Gbps and 300km at 400Gbps.
Hardware details
The WaveLogic Ai is implemented using a 28nm semiconductor process known as fully-depleted silicon-on-insulator (FD-SOI). "This has much lower power than a 16nm or 18nm FinFET CMOS process," says Xenos. (See Fully-depleted SOI vs FinFET)
Using FD-SOI more than halves the power consumption compared to Ciena’s existing WaveLogic 3 coherent devices. "We did some network modelling using either the WaveLogic 3 Extreme or the WaveLogic 3 Nano, depending on what the network requirements were," says Xenos. "Overall, it [the WaveLogic Ai] was driving down [power consumption] more than 50 percent." The WaveLogic 3 Extreme is Ciena's current flagship coherent DSP-ASIC while the Nano is tailored for 100-gigabit metro rates.
Other Ai features include support for 400 Gigabit Ethernet and Flexible Ethernet formats. Flexible Ethernet is designed to support Ethernet MAC rates independent of the Ethernet physical layer rate being used. Flexible Ethernet will enable Ciena to match the client signals as required to fill up the variable line rates.
Further information:
SOI Industry Consortium, click here
STMicroelectronics White Paper on FD-SOI, click here
Other coherent DSP-ASIC announcements in 2016
Infinera's Infinite Capacity Engine, click here
Nokia's PSE-2, click here
Imec gears up for the Internet of Things economy
It is the imec's CEO's first trip to Israel and around us the room is being prepared for an afternoon of presentations the Belgium nanoelectronics research centre will give on its work in such areas as the Internet of Things and 5G wireless to an audience of Israeli start-ups and entrepreneurs.
Luc Van den hove
iMinds merger
Imec announced in February its plan to merge with iMinds, a Belgium research centre specialising in systems software and security, a move that will add 1,000 staff to imec's 2,500 researchers.
At first glance, the world-renown semiconductor process technology R&D centre joining forces with a systems house is a surprising move. But for Van den hove, it is a natural development as the company continues to grow from its technology origins to include systems-based research.
"Over the last 15 years we have built up more activities at the system level," he says. "These include everything related to the Internet of Things - our wireless and sensor programmes; we have a very strong programme on biomedical applications, which we sometimes refer to as the Internet of Healthy Things - wearable and diagnostics devices, but always leveraging our core competency in process technology."
Imec is also active in energy research: solar cells, power devices and now battery technology.
For many of these systems R&D programmes, an increasing challenge is managing data. "If we think about wearable devices, they collect data all the time, so we need to build up expertise in data fusion and data science topics," says Van den hove. There is also the issue of data security, especially regarding personal medical data. Many security solutions are embedded in software, says Van den hove, but hardware also plays a role.
Imec expects the Internet of Things to generate massive amounts of data, and more and more intelligence will need to be embedded at different levels in the network
"It just so happens that next to imec we have iMinds, a research centre that has top expertise in these areas [data and security]," says Van den hove. "Rather than compete with them, we felt it made more sense to just merge."
The merger also reflects the emergence of the Internet of Things economy, he says, where not only will there be software development but also hardware innovation: "You need much more hardware-software co-development". The merger is expected to be completed in the summer.
Internet of Things
Imec expects the Internet of Things to generate massive amounts of data, and more and more intelligence will need to be embedded at different levels in the network.
"Some people refer to it as the fog - you have the cloud and then the fog, which brings more data processing into the lower parts of the network," says Van den hove. "We refer to it as the Intuitive Internet of Things with intelligence being built into the sensor nodes, and these nodes will understand what the user needs; it is more than just measuring and sending everything to the cloud."
Van den hove says some in the industry believe that these sensors will be made in cheap, older-generation chip technologies and that processing will be performed in data centres. "We don't think so," he says. "And as we build in more intelligence, the sensors will need more sophisticated semiconductors."
Imec's belief is that the Internet of Things will be a driver for the full spectrum of semiconductor technologies. "This includes the high-end [process] nodes, not only for servers but for sophisticated sensors," he says.
"In the previous waves of innovation, you had the big companies dominating everything," he says. "With the Internet of Things, we are going to address so many different markets - all the industrial sectors will get innovation from the Internet of Things." There will be opportunities for the big players but there will also be many niche markets addressed by start-ups and small to medium enterprises.
Imec's trip to Israel is in response to the country's many start-ups and its entrepreneurship. "Especially now with our wish to be more active in the Internet of Things, we are going to work more with start-ups and support them," he says. "I believe Israel is an extremely interesting area for us in the broad scope of the Internet of Things: in wireless and all these new applications."
Herzliya
Semiconductor roadmap
Van den hove's background is in semiconductor process technology. He highlights the consolidation going on in the chip industry due, in part, to the CMOS feature nodes becoming more complex and requiring greater R&D expenditure to develop, but this is a story he has heard throughout his career.
"It always becomes more difficult - that is Moore's law - and [chip] volumes compensate for those challenges," says Van den hove. When he started his career 30 years ago the outlook was that Moore's law would end in 10 years' time. "If I talk to my core CMOS experts, the outlook is still 10 years," he says.
Imec is working on 7nm, 5nm and 3nm feature-size CMOS process technologies. "We see a clear roadmap to get there," he says. He expects the third dimension and stacking will be used more extensively, but he does not foresee the need for new materials like graphene or carbon nanotubes being used for the 3nm process node.
Imec is pursuing finFET transistor technology and this could be turned 90 degrees to become a vertical nanowire, he says. "But this is going to be based on silicon and maybe some compound semiconductors like germanium and III-V materials added on top of silicon." The imec CEO believes carbon-based materials will appear only after 3nm.
"The one thing that has to happen is that we have a cost-effective lithography technique and so EUV [extreme ultraviolet lithography] needs to make progress," he says. Here too he is upbeat pointing to the significant progress made in this area in the last year. "I think we are now very close to real introduction and manufacturing," he says.
We see strong [silicon photonics] opportunities for optical interconnect and that is one of our biggest activities, but also sensor technology, particularly in the medical domain
Silicon Photonics
Silicon photonics is another active research area with some 200 staff at imec and at its associated laboratory at Ghent university. "We see strong opportunities for optical interconnect and that is one of our biggest activities, but also sensor technology, particularly in the medical domain," he says.
Imec views silicon photonics as an evolutionary technology. "Photonics is being used at a certain level of a system now and, step by step, it will get closer to the chip," he says. "We are focussing more on when it will be on the board and on the chip."
Van den hove talks about integrating the photonics on a silicon interposer platform to create a cost-effective solution for the printed circuit board and chip levels. For him, first applications of such technology will be at the highest-end technologies of the data centre.
For biomedical sensors, silicon photonics is a very good detector technology. "You can grow molecules on top of the photonic components and by shining light through them you can perform spectroscopy; the solution is extremely sensitive and we are using it for many biomedical applications," he says.
Looking forward, what most excites Van den hove is the opportunity semiconductor technology has to bring innovation to so many industrial sectors: "Semiconductors have created a fantastic revolution is the way we communicate and compute but now we have an opportunity to bring innovation to nearly all segments of industry".
He cites medical applications as one example. "We all know people that have suffered from cancer in our family, if we can make a device that would detect cancer at a very early stage, it would have an enormous impact on our lives."
Van den hove says that while semiconductors is a mature technology, what is happening now is that semiconductors will miniaturise some of the diagnostics devices just like has happened with the cellular phone.
"We are developing a single chip that will allow us to do a full blood analysis in 10 minutes," he says. DNA sequencing will also become a routine procedure when visiting a doctor. "That is all going to be enabled by semiconductor technology."
Such developments is also a reflection of how various technologies are coming together: the combination of photonics with semiconductors, and the computing now available.
Imec is developing a disposable chip designed to find tumour cells in the blood that requires the analysis of thousands of images per second. "The chip is disposable but the calculations will be done on a computer, but it is only with the most advanced technology that you can do that," says Van den hove.