coherent DSPs

• Ciena’s WaveLogic 5 coherent digital signal processor family comprises the Extreme and Nano chips

• The WaveLogic 5 Extreme maximises optical capacity and transmission reach while the WaveLogic 5 Nano is targeted at compact, power-conservative applications

Advancing coherent optical transmission performance; targeting the emerging coherent pluggable market; selling modules directly, and the importance of being more vertically integrated. All these aspects were outlined by Cisco to explain why it intends to buy the coherent optical transmission specialist, Acacia Communications; a deal that is set to be completed in the spring of 2020.

But such strategic thinking is being pursued by Ciena with its next-generation WaveLogic 5 family of coherent DSPs.

The WaveLogic 5 continues Ciena’s tradition of issuing a coherent digital signal processor (DSP) family approximately every three years: Ciena announced the WaveLogic 3 in 2012 and the WaveLogic Ai in 2016. (Add links).

The company has managed to maintain its three-yearly cadence despite the increasing sophistication of each generation of coherent DSP. For example, the WaveLogic 5 Extreme will support 800 gigabits-per-wavelength, double Ciena’s WaveLogic Ai that has been shipping for nearly two years.

Kim Roberts, vice president of WaveLogic science, says Ciena has managed to deliver its coherent DSPs in a timely manner since much of the algorithmic development work was done 5-6 years ago. The issue has been that certain features developed back then could not be included within the WaveLogic Ai.

WaveLogic 5 is implemented using a 7nm FinFET CMOS process whereas the WaveLogic Ai uses a 28nm specialist CMOS process known as fully-depleted silicon-on-insulator (FD-SOI).

“Seven-nanometer CMOS, due to its density and low heat, allows us to implement things that didn’t make the cut for the WaveLogic Ai,” says Roberts.

The company has a ‘suitcase of ideas’, he says, but not all of the concepts make it into any one generation of chip. “They have to justify performance versus schedule versus heat [generated],” says Roberts. “As we improve the technology, more features make the cut.”

And there are developments that will be included in future designs: “We keep refilling the suitcase,” says Roberts.

NAMING

Ciena first used the Extreme and Nano nomenclature with the WaveLogic 3. In contrast, the WaveLogic Ai, when launched in 2016, was a single-chip targeting the high-end. Ciena chose to change the naming scheme with the Ai since the chip signified a shift with features such as network monitoring.

However, Ciena highlights a key difference between the WaveLogic 3 and WaveLogic 5 families. The WaveLogic 3 Extreme and the WaveLogic 3 Nano could talk to each other on appropriate spans. In contrast, the two WaveLogic 5 chips are distinct. “They are not designed to interwork,” says Roberts.

NETWORKING TRENDS

Telecom service providers are investing in their networks to make them more adaptive. They want their networks to be scalable and programmable, says Ciena.

The operators also want to better understand what is happening in their networks and that requires collecting data, performing analytics and using software to configure their networks in an automated way.

“How do you get there? It is all about coherent technology,” says Helen Xenos, senior director, portfolio marketing at Ciena. “It is a critical element that is helping operators scale their networks.”

By enhancing the traffic-carrying capacity of fibre, coherent technology enables operators to reduce transport costs. “It allows them to be more competitive as they can do more with the hardware they deploy,” says Xenos.

Both telcos and cable operators are also applying coherent technology to new applications in their networks such as access.

These transport needs are causing a divergence in requirements.

One is to keep advancing optical performance in terms of the spectral efficiency and the traffic-carrying capacity of links. This is what the WaveLogic 5 Extreme tackles.

The second requirement - producing a compact coherent design for the network edge - is addressed by the WaveLogic 5 Nano.

For access designs, what is important is a compact design where the optics and the DSP can operate over an extended temperature range.

The Nano also addresses the hyperscalers’ need to connect their distributed data centres across a metro. “They need high capacity - 400 gigabits - and short-reach connectivity,” says Xenos. “It really needs to be the smallest footprint to maximise density.”

VERTICAL INTEGRATION

In addition to unveiling the WaveLogic 5 Extreme and Nano ICs, Ciena has outlined how it is more vertically integrated after investing in optics. In 2016, Ciena acquired the high-speed photonics division of Teraxion, gaining expertise in indium phosphide and silicon photonics expertise. {add link}.

Ciena is also now selling coherent optical modules. Gazettabyte revealed last year that Ciena was planning to sell modules using its own optics and WaveLogic technologies. {add link}

The company has no preference regarding indium phosphide and silicon photonics and uses what is best for a particular design.

“Silicon photonics buys you ease-of-manufacturing and cost; indium phosphide is what you need for 800 gigabits,” says Xenos.

Ciena stresses, however, that there is no simple formula as to when each is preferred. In terms of size and heat, silicon photonics has a strong advantage. “In terms of performance, you get better performance in some instances with indium phosphide and then there are overlaps because you bring in cost and other constraints,” says Roberts. “So there is no simple divide.”

“As we move forward, we are going to see an increasing percent of Ciena-custom components in WaveLogic coherent modems,” says Xenos.

EXTREME

The WaveLogic 5 Extreme introduces several developments. It operates at specific baud rates ranging from 60 to 95 gigabaud. The baud rates are chosen so that both fixed-grid 100GHz channels and flexible grid ones are supported.

“For the best performance, you have flexible grid when 95 gigabaud is the primary baud rate,” says Roberts.

It is also Ciena’s first coherent DSP that uses probabilistic constellation shaping, a coding scheme used to achieve granular capacity increments. {add link}

“From 200 gigabits to 800 gigabits [in 25-gigabit increments], optimised over any path or the available margin,” says Roberts. “But what is unique about this is that it is optimised for non-linear propagation.”

Initially, the products using the WaveLogic 5 Extreme will use 50-gigabit increments. “This is what is required to service customers’ client requirements today: ten gigabits and multiples of 100-gigabit clients,” says Xenos.

The DSP uses four-wave frequency-division multiplexing to mitigate non-linear impairments, particularly beneficial for sub-sea systems.

Ciena says the four-wave frequency-division multiplexing is achieved electrically, reducing the optics to a minimum. “One laser and one modulator are used, so all the [cost-saving] economics of a single optical wavelength,” says Roberts. “But it has the non-linear performance of four tightly-coupled electrical systems.”

Ciena has also added an improved forward-error correction (FEC) scheme - a ‘throughput-optimised FEC’ - that uses variable overhead bits depending on the client rate.

“It will handle 8.6 percent errors compared to what we used in the WaveLogic Ai which handles 3.5 percent errors,” says Roberts. “So it is a decibel better.”

The Extreme chip also has improved link-monitoring capabilities. It monitors the signal-to-noise per channel as well as quantifies the non-linear contributions. “It helps people to understand what is happening in the network and create algorithms to optimise the capacity across the network,” says Xenos.

PROBABILISTIC CONSTELLATION SHAPING

Probabilistic shaping is used to improve the optical performance by lowering the signal energy by not using all the constellation points. Unless, that is, the full data rate is used and then all the constellation points are needed.

The degree of probabilistic shaping used is determined for each link. The parameters used to determine the probabilistic shaping are the amount of dispersion on the link, the span’s reach, and the transmitted client rate.

“The modem will measure what is going on in the link and the customer or some higher-level software will say what the client rate is,” says Roberts. “The modem will then figure out how to do the best non-linear probabilistic shaping to support that rate on the link.”

Roberts says other firms’ probabilistic shaping use one symbol at a time whereas Ciena use blocks, each comprising 128 symbols. “A bigger number would be better but I'm limited by my hardware,” says Roberts.

The 128 symbols equate to 1024 bits: four magnitude bits using 64-ary quadrature amplitude modulation (64-QAM) multiplied by two, one for each polarisation.

This means there are a total of 2^1024 combinations of 1024-bit sequences that could be sent. However, when sending a 400 Gigabit Ethernet (GbE) client signaland, for the benefit of explanation, assuming that 555 bits are needed to carry the data payload and the overhead, the number of possible bit sequences is trimmed to 2^555.

This is still a fantastically huge number but the DSP can work out which are the best 555-bit sequences to send based on them having the most tolerance to linear and non-linear interference.

“The ones that play nicely with their neighbours such that they cause the minimum non-linear degradation on the neighbouring wavelengths and on the other symbols,” explains Roberts.

Ciena is not forthcoming as to how it calculates the best sequences. “Ciena’s algorithms decide which ones are best,” says Xenos. “This is one of our key differentiators.”

The result is that, depending on the fibre type, a 1.5dB performance improvement is achieved for the non-linear characteristics.

“It allows more capacity to be chosen by the customer on that same link,” says Roberts. “With 25-gigabit steps in client rate, the customer can choose to spend the margin on sending more bits.”

Operating the Extreme at 95GBd, a reach of 4,000 km is possible at 400 gigabits and at 600 gigabits, the reach is 1,000 km (see table).

WAVELOGIC 5 NANO

The WaveLogic Nano supports 100-gigabit to 400-gigabit wavelengths and is aimed at applications that need compact designs that generate the least heat.

One application is to enable cable operators to move optics closer to the user and that must operate over an extended temperature range. Here, a packet platform is used that will support line interworking as equipment from different vendors may be at each end of the link.

Another requirement is operating over multiple spans in a metro. Here, compact equipment and low power are more important than spectral efficiency but it is still a challenging environment, says Ciena. Hundreds of nodes may be talking to each other and there may be cascaded reconfigurable optical add-drop multiplexers (ROADMs) with different fibre types making up the network.

A third application is single-span data centre interconnect where achieving the highest density on routers is key. This is the application the 400-gigabit, at least 80km 400ZR specification developed by the Open Internetworking Forum will address.

“The design that we are doing for the WaveLogic 5 Nano for 400ZR is to fit into a QSFP-DD,” says Xenos. “If there is a need for an OSFP [pluggable module], we will offer OSFP.”

Ciena also expects to offer a Nano-based CFP2-DCO module, which will outperform the ZR in terms of reach and features, for more demanding metro applications.

Another new segment requiring coherent optics is 4G and 5G access. “It is to be determined what type of platform is the winning solution in this environment,” says Xenos.

MAKING MODULES

Ciena first made its coherent DSP available to third parties in 2017 when it signed an agreement with Lumentum, NeoPhotonics and at the time Oclaro (since acquired by Lumentum) to use its WaveLogic Ai in their modules.

Now Ciena is selling directly the full coherent modem: the DSP and the optics. This is why Ciena created its Optical Microsystems unit in late 2017.

CMOS PROCESS

Moving to a 7nm FinFET CMOS process delivers several benefits.

It generates much lower heat than the WaveLogic Ai’s 28nm FD-SOI process. It also has a lower quiescent current, the current dissipated independent of whether the chip’s logic is active or not. And 7nm CMOS delivers much greater circuit density: the functionality that can be crammed into a square micrometre of silicon.

“So, a low power [consumption] on features you are not using, and we can include features that if you can't afford the heat, you can turn them off,” says Roberts.

It will offer its Nano in the form of pluggable modules, the WaveLogic Ai as a 5x7-inch module, and the WaveLogic 5 Extreme in another module form factor that will have its own interface. “These would all be viable optics,” says Xenos.

Availability

The first Wave Logic 5 Nano products will appear in the second half of this year while the first Extreme-based products will be available at the end of this year. The 400ZR coherent pluggable module is expected to be available in the first half of 2020.