Acacia looks to co-package its coherent PIC and DSP-ASIC
- Acacia Communications is working to co-package its coherent DSP and its silicon photonics transceiver chip.
- The company is also developing a digital coherent optics module that will support 400 gigabit.
Acacia Communications is working to co-package its coherent DSP and its silicon photonics transceiver chip. The line-side optical transceiver company is working on a digital coherent optics module that will support 400 gigabits.
Acacia announced last November that it was sampling the industry’s first CFP2 Digital Coherent Optics (CFP2-DCO) that supports 100- and 200-gigabit line rates. The CFP2-DCO integrates the DSP and its silicon photonics chip within a CFP2 module, which is half the size of a CFP module, with each chip packaged separately.
The CFP2-DCO adds to the company’s CFP2-ACO design that was announced a year ago. In the CFP2-ACO, the CFP2 module contains just the optics with the DSP-ASIC chip on the same line card connected to the module via a special high-speed interface connector.
Now, Acacia is working to co-package the two chips, which will not only improve the performance of its CFP2-DCO but also enable new, higher-performance optical modules such as a 400-gigabit DCO. The Optical Internetworking Forum announced a new implementation agreement last December for an interoperable 400-gigabit ZR (80km) coherent interface.
Both [the DSP and silicon photonics chip] are based on CMOS processes. The next step for Acacia is to bring them into a single package.
Portfolio upgrades
Acacia has also upgraded its existing portfolio of coherent transceivers. The company has integrated the enhanced silicon photonics coherent transceiver in its AC100-CFP and its AC-400 5x7-inch modules.
The silicon-photonics transceiver achieves a more efficient coupling of light in and out of the chip and uses an improved modulator driver design that reduces the overall power consumption. The design also supports flexible grid, enabling channel sizes of 37.5GHz in addition to fixed-grid 50GHz channels.
The resulting AC100-CFP module has a greater reach of 2,500km and a lower power consumption than the first generation design announced in 2014. The enhanced PIC has also been integrated within the AC-400. The AC-400, announced in 2015, integrates two silicon photonics chips to support line rates of 200, 300 and 400 gigabits.
CFP2-DCO
Acacia is using the coherent transceiver photonic integrated circuit (PIC), first used in its CFP2-ACO, alongside a new coherent DSP to integrate the optics and DSP within the compact CFP2.
“The third-generation PIC is a mini PIC; in a gold box that is about the size of a dime, which is a third of the size of our original PIC,” says Benny Mikkelsen, founder and CTO of Acacia.
One design challenge with its latest DSP was retaining the reach of the original DSP used in the AC100-CFP while lowering its power consumption. Having an inherently low-power coherent DSP design in the first place is one important factor. Mikkelsen says this is achieved based on several factors such as the DSP algorithms chosen and how they are implemented in hardware, the clock frequencies used within the chip, how the internal busses are implemented, and the choice of bits-per-symbol used for the processing.
The resulting DSP’s power consumption can be further reduced by using an advanced CMOS process. Acacia uses a 16nm CMOS process for its latest DSP.
Other challenges to enable a CFP2-DCO module include reducing the power consumption of the optics and reducing the packaging size. “The modulator driver is the piece part that consumes the most power on the optics side,” says Mikkelsen.
Acacia's CFP2-DCO supports polarisation multiplexing, quadrature phase-shift keying (PM-QPSK) for 100 gigabits, and two modulation schemes: polarisation multiplexing, 8-ary quadrature amplitude multiplexing (PM-8QAM) and 16-ary QAM - for 200-gigabit line rates. In contrast, its -ACO supports just PM-QPSK and PM-16QAM.
At 100 gigabits, the DSP consumes about half the power of the Sky DSP used in the original AC100. Using PM-8QAM for 200 gigabits means the new DSP and optics support a higher baud rate - some 45 gigabaud compared to the traditional 32-35 gigabaud used for 100 and 200-gigabit transmission. However, while this increases the power consumption, the benefit of 8QAM is a 200-gigabit reach beyond 1,000km.
Mikkelsen stresses that a key reason the company can achieve a CFP2-DCO design is having both technologies in-house: “You can co-optimise the DSP and the silicon photonics”.
We think, at least in the near term, that the OSPF module seems to be a good form factor to work on
ACO versus DCO
Since Acacia now offers both the CFP2-ACO and CFP2-DCO modules, it is less concerned about how the relative demand for the two modules develops. “We don’t care too much which one is going to have the majority of the market,” says Mikkelsen. That said, Acacia believes that the CFP2-DCO market will become the larger of the two.
When the CFP2-ACO was first considered several years ago, the systems vendors and optical module makers shared a common interest. Systems vendors wanted to use their custom coherent DSP-ASICs while the -ACO module allowed component makers that didn't have the resources to develop their own DSP to address the market with their optics. It was also necessary to separate the DSP and the optics if the smaller CFP2 form factor was to be used.
But bringing CFP2-ACOs to volume production has proved more difficult than first envisaged. The CFP2-DCO is far easier to use, says Mikkelsen. The module can be plugged straight into equipment whereas the CFP2-ACO must be calibrated by a skilled optical engineer when a wavelength is first turned up.
Future work
Acacia is now looking at new module form factors and new packaging technologies. “Both [the DSP and silicon photonics chip] are based on CMOS processes,” says Mikkelsen. “The next step for Acacia is to bring them into a single package.”
In addition to the smaller size, a single package promises a slightly lower power consumption as well as manufacturing cost advantages. “We also expect to see higher performance once the DSP and optics are sitting next to each other which we believe will improve signal integrity between the two,” says Mikkelsen.
Acacia is not waiting for any industry challenges to be overcome for a single-package design to be achieved. The company points out that its silicon photonics chip is not temperature sensitive, aiding its co-packaging with the DSP.
Acacia is working on a 400-gigabit DCO design and is looking at several potential module types. The company is a member of the OSFP module MSA as well as the Consortium of On-Board Optics (COBO) which has started a coherent working group. “We think, at least in the near term, that the OSPF module seems to be a good form factor to work on,” says Mikkelsen.
Acacia uses silicon photonics for its 100G coherent CFP
Acacia Communications has revealed the innards of its 100 Gig coherent pluggable module for metro networks. The AC-100 CFP combines a low-power DSP-ASIC with a silicon-photonics-based optics chip. The CFP's reach is 80km to 1,200km, and its power consumption is 24-26W, well within the pluggable's maximum power profile of 32W.
The power consumption of the AC-100 CFP, and its main components, and the target power consumptions of the components needed for a digital CFP2. Source: Gazettabyte
The start-up says it is shipping samples of the AC-100 CFP and already has 15 customers. "That includes some of the bigger [systems] players that have their own internal DSP," says Raj Shanmugaraj, CEO of Acacia. "The coherent CFP is not their focus; they are going after long-haul."
The start-up is shipping samples of the AC-100 CFP and already has 15 customers
Acacia chose to develop it own DSP chips as it sees the technology as core for coherent-based optical transmission. "That is where we see the big market," says Shanmugaraj. "We have a 100 Gig [MSA] that has been shipping, and a 200-400 Gig product that is in development."
DSP-ASIC and silicon photonics
The DSP-ASIC for the AC-100 CFP is Acacia's second chip design. Its first, a DSP-ASIC for its long-haul 5x7-inch OIF MSA transponder, is implemented using a 40nm CMOS process. The latest metro DSP-ASIC uses 28nm CMOS.
The DSP-ASIC includes analogue-to-digital (A/D) and digital-to-analogue (D/A) converters and a serialiser/ deserialiser (Serdes). Also on-chip is the digital signal processor (DSP) that implements soft-decision, forward error correction (SD-FEC) and compensation algorithms for chromatic and polarisation-mode dispersion.
Other DSP-ASIC features include spectral shaping for flexible grid transmission. "The signal processing on the transmit side fits in the one ASIC," says Benny Mikkelsen, CTO at Acacia. Also on-chip are a 100 Gig OTN (Optical Transport Network) framer and a microprocessor to manage the DSP-ASIC and the overall CFP.
The DSP-ASIC consumes 12-14W: the A/D, D/A converters and Serdes consume 5W, while the DSP consumes 7W for an 80km link - the 100 Gig equivalent of the -ZR spec - and 9W for 1,200km transmission due to the more powerful SD-FEC needed.
Mikkelsen says achieving a low-power ASIC requires several approaches. The SD-FEC is designed to be extremely low power, he says, as is the dispersion compensation: "Not just the algorithms but how we code the algorithms." Also, how the ASIC's circuitry is laid out impacts power consumption.
Acacia's engineers have also developed a silicon-photonics chip that combines the coherent transmitter and receiver optics. "The PIC [photonic integrated circuit] is the first silicon-photonics chip targeted at metro/ metro-regional," says Shanmugaraj. "It is an IC that has all the components except the laser, and is co-packaged in a gold box with the drivers and trans-impedance amplifiers."
Acacia's PIC is monolithic; all the functional blocks are implemented in silicon rather than combined silicon and III-V materials, a technique known as heterogeneous integration.
Using silicon photonics rather than indium phosphide has advantages, says Shanmugaraj. Silicon photonics benefits from mature CMOS processes developed for the semiconductor industry: "With the large silicon wafers, you can have thousands of these silicon PICs on them," he says.
Acacia tests the PICs directly on the wafer. This avoids having to dice the wafer and package each die before testing. "We also don't need thermal control [of the chip] or hermetic packaging," says Shanmugaraj. With indium phosphide, the modulators do require thermal cooling, adding to the design complexity and the power consumption. The PIC is 10mm long and consumes less than 5W.
The AC-100 CFP is expected to cost less than half the 5x7-inch 100 Gig coherent MSA which sells for $20,000. "One of the biggest pain points in metro is cost, if you ask most of the service providers," says Shanmugaraj. At below $10,000, the coherent CFP will be cost-competitive with the 100 Gig direct-detection CFP that uses 4x25 Gig wavelengths. However, the 100 Gig direct-detection CFP continues to come down in price as more products come to market.
Roadmap
Acacia will continue to address long-haul and metro, each requiring its own ASIC. "We don't believe that you can have one ASIC that serves both submarine and the metro," says Mikkelsen. In turn, silicon photonics will be used for pluggables while discrete optics will be used for the more demanding submarine.
The company says it is developing a multi-core ASIC to support super-channels and 16-QAM modulation for 200 Gig and 400 Gig transmission. The company says it will provide more details of its flexible, adaptive-rate ASIC at ECOC, to be held in September this year.
The company's product roadmap also features a co-packaged DSP-ASIC and PIC that will fit within a CFP2. Achieving such a pluggable, dubbed a digital CFP2, require a further halving of the DSP-ASIC's power consumption. This, says Acacia, is achievable using the next CMOS process node after 28nm.
The advantages of a digital CFP2 compared to a CFP2 with optics only, with the DSP-ASIC on the line card, include using the DSP-ASIC only when it is needed. When a fault occurs, the relevant pluggable can be replaced rather than having to remove the complete line card. Lastly, new functionality in the DSP-ASIC can be introduced by plugging in the new CFP2 pluggable compared with having to redesign the line card.
See also:
Transmode adopts 100 Gigabit coherent CFPs, click here
ClariPhy samples a 200 Gigabit coherent DSP-ASIC, click here