Russ Esmacher, Senior Vice President and General Manager of the Data Center Interconnect business at Marvell, talks about 800 gigabit ZR+ coherent pluggable modules, the path to 1600 gigabit coherent, and why the pendulum never stops swinging between the digital signal processor and the optics.
Russ Esmacher (pictured) has spent much of his career at the sharp end of coherent optics.
He worked at Cisco and Nokia before joining Infinera, where he spent 5 years and where he helped with its sale to Nokia.
He then took what he describes as time off. It lasted three days.
Matt Murphy, Chairman and CEO of Marvell, and Sandeep Bharathi, President of the Data Center Group at Marvell, asked him to lead the company’s Data Center Interconnect business.
Two months in, Esmacher is direct about the company’s position: Marvell invented the coherent pluggable space with 100 gigabit, he says, and now leads the market.
AI’s impact on coherent pluggables
The rapid scaling of AI workloads has reshaped the coherent pluggable landscape.
According to Esmacher, the last three calendar quarters of 2025 saw demand for 800-gigabit pluggables – 800ZR+ – accelerate with the new application of ‘scale-across’, using optical networking to share AI workloads between data centres.
Classical data centre interconnect has been about linking data centres up to 120 kilometres apart. Scale-across changes that, in the bandwidth between sites and the reach which can be 100km up to 1,000km.
Hyperscalers, under pressure to reserve power for compute and training, pushed the optical industry to bring 800ZR+ forward by roughly 18 months. “They prefer to use power for computing or training, not transport,” says Esmacher. “And so we really accelerated the timeline.”
The huge demand has created a supply chain challenge; not for Marvell, Esmacher notes, but for others entering the space.
“The demand is way outstripping the supply right now,” he says. “It’s a steep ramp; it’s a great problem to have.”
One coherent DSP, several applications
The 800-gigabit ZR+ coherent pluggable has benefited from what the industry learned from the limitations of extending the OIF’s 400-gigabit 400ZR standard.
At 400 gigabits, extending the reach beyond the original ZR design of 120km proved difficult due to the legacy carrier reconfigurable optical add-drop multiplexer (ROADM) passbands, with their associated accumulated impairments, limited optical performance. And combining PIC-based amplification with a 7-nanometre CMOS digital signal processor (DSP) in a pluggable module made the devices run too hot for practical deployment.
The lesson, says Esmacher, was to invest in advanced CMOS nodes so that higher performance, including the use of probabilistic constellation shaping, could fit within a pluggable’s power envelope.
The result is a DSP that serves two roles: 800ZR+, which a reach of 1,000km to 1,500km, and for 400 gigabit using quadrature phase-shift keying (QPSK) to enable 4,000km spans or more.
The 800ZR+ designs are more difficult to make because the optical performance is much higher — the analogue bandwidth of the components and the associated radio frequency (RF) are higher — due to the doubling of the symbol rate up to 135 gigabaud.
“Essentially, we’re squeezing long-haul technology from five years ago into a 30-watt body,” says Esmacher. “Now, it is deployment time.”
New requirements keep emerging too, such as the need for MACsec encryption. As training data increasingly leaves data centres, sovereignty and security concerns are driving demand for encryption regardless of the coherent pluggable’s reach: 100km or 1,000km.
1600 gigabit coherent outlook: two DSPs, not one
Looking ahead to the OIF’s 1600-gigabit coherent standards, Esmacher says 1600ZR and 1600ZR+ pluggable applications will be released at different times.
The 1600ZR standard is further along and closer to market, driven by hyperscaler demand for the shorter-reach application.
Several large hyperscalers are waiting for it, says Esmacher, who expects ZR to account for the larger share of volume — as much as 65-70 per cent — with ZR+ accounting for the remainder.
Marvell believes that the two 1600-gigabit coherent pluggable applications will require separate DSP designs. ZR must be optimised for power and time-to-market, whereas ZR+ must be optimised for optical performance.
Trying to build a single DSP that serves both introduces compromises. “If you’re going to do ZR, it’s power, power, power,” says Esmacher.
The 1600G ZR+ design is expected to use multiple digital subcarriers — two, according to OIF discussions — which would add power and complexity to the DSP, overkill for the shorter-reach application.
1600 gigabit Coherent Light: multiple choices
The emerging ‘Coherent light’ (1600CL) application for intra-data-centre links also draws Esmacher’s attention.
He acknowledges that a de-featured coherent DSP — what he informally calls “ZR minus” — is one path, but not the only one. Two 800G PAM-4 channels could also serve the same application, depending on cost and power trade-offs.
“If I can get there with lower power and cost using two by 800 PAM-4, I’ll do it,” says Esmacher.
He points to Marvell’s position as the market leader in PAM-4, a capability shared by coherent companies such as Acacia.
The 1600CL standard work at the OIF is important, says Esmacher, but the industry should recognise that there are multiple paths.
Pluggables, line systems, and data centre densification
Esmacher frames the broader market shift as a deceptively simple question: are data centres moving further apart or closer together? The answer is closer together, he says.
At first glance, this is counterintuitive, since scale-across has arisen this way. But overall, there is a densification of data centres, with the pluggable transceivers spectral-efficient enough to do the job previously reserved for embedded coherent transponders. And now the pluggables consume significantly less power.
The implication is that embedded coherent engines, once the default for terrestrial long-haul, are increasingly confined to subsea and the longest routes.
However, because pluggables are less spectrally efficient than high-performance embedded engines, moving the same volume of data between sites requires more line system capacity.
Esmacher sees the densification of open line systems — from single-rail to multi-rail architectures — as the key enabler. “That’s where all the emphasis for the next two years is going to go,” he says.
The largest hyperscale deployers of line systems appear to be moving toward C+L bands, though some may opt for high-density C-bands alone.
DSP, optics, and the path to 3.2T terabit coherent
Esmacher likens coherent innovation to a pendulum swinging between the digital and the analogue domains.
When PIC-based amplification emerged around 2018, the pressure was on the DSP: squeezing algorithms into smaller node CMOS. The optics side — silicon photonics modulators and indium phosphide lasers — could coast on existing platforms.
But at 1.6 terabit, the pendulum has swung toward the optics. Silicon photonics modulators are approaching bandwidth limits, potentially prompting a shift to new materials such as thin-film lithium niobate. That transition brings an entirely new foundry and manufacturing ecosystem, but one that starts not at low volumes but high ones.
“It sounds easy going from silicon photonics to thin film lithium niobate,” says Esmacher. “But it’s a whole new ecosystem.”
For 3.2 terabit coherent, he expects the pendulum to swing back toward the DSP, with pressure on the CMOS process node to fit the DSP within a liquid-cooled, 40-to-50-watt power envelope. That likely means moving to a 1.4-nanometre-or-below CMOS process.
But before 3.2 terabit coherent arrives, Esmacher expects 1.6 terabit coherent to have a long market life — not because of the DSP, but because the optical ecosystem needs time to mature.
“These pendulums swing in coherent between the digital and the analogue,” says Esmacher. “At 1.6T, all the pressure is on the analogue. At 3.2T, I think it swings back to the DSP.”