Silicon photonics grapples with 3D packaging demands

Hesham Taha (pictured), CEO of start-up Teramount, is more upbeat about silicon photonics than ever. But, as he outlines, challenges remain.

Hesham Taha is putting in the miles. The CEO of Teramount has been travelling to the East and West to meet with companies.

Termount is working closely with customers and partners adopting its technology that adds fibre to silicon photonics chips. 

"We're shipping units to customers and partners, and we need to be close to them as they integrate our components and address the challenges of integration," says Taha.

Teramount

For Taha, connecting fibre to a silicon photonics chip inside a pluggable optical transceiver is relatively straightforward.

Far more challenging is when the optical engine and chip are packaged together, known as co-packaged optics. Such a tight coupling raises reliability challenges.

The optical engine is close to the large, heat-generating chip, introducing manufacturing and reliability issues. Also, the fibre-connect to the optical engine inside the package must be scalable. Scaling is key because with each chip generation - whether an AI accelerator or a switch chip - the input-output (I/O) requirements grow.

Teramount’s technology couples the fibre to the silicon photonics chip using a photonic plug and photonic bump. 

The photonic plug holds the fibres and couples them to the silicon photonics chip via a photonic bump, a component made during the silicon photonics wafer’s processing.

The photonic bump has two elements: a wideband deflector and a lens mirror for beam expansion. Expanding the light beam enables larger assembly tolerances.

The resulting wafer-level manufacturing may be more complicated, says Taha, but the benefits include relaxed tolerances in the assembly, wideband surface coupling, and the testing of the wafer and the die.

The photonic bump-and-plug combination also enables detachable optics for co-packaged optics designs, benefitting their manufacturing. (For more about Teramount’s technology, click here)

Teramount's detachable fibre connector technology

Silicon Photonics meets semiconductor thinking

Taha sees silicon photonics as a platform that enables the integration of optical functions at the wafer scale using standard semiconductor manufacturing techniques.

“It [silicon photonics design] has the same way of thinking as semiconductor people: chip designers, foundries, and packaging people,” says Taha. The result is that silicon photonics is bringing optics to chip design.

The growing maturity of the technology, and the emergence of foundries such as TSMC, GlobalFoundries, Tower Semiconductor, Intel, and ST Microelectronics offering silicon photonics, means that companies with photonic designs can be fabless; a model that has benefitted the chip industry.

Photonic chip designers can use a large foundry’s process design kit (PDK) and send off their silicon photonics designs to be manufactured in volume.

As for co-packaged optics, Taha sees it as a key in the evolution of silicon photonics. Co-package optics is the realisation of silicon photonics whereby optics is integrated next to advanced semiconductor chips.

Industry developments

The growing interest in silicon photonic and co-packaged optics is also evident in some recent announcements, driven by the AI compute scaling needs.

ST Microelectronics unveiled its 300mm wafer PIC100 silicon photonics technology. ST Microelectronics was active in silicon photonics 10 years ago and has returned due to the AI opportunity. 

Marvell announced it offers a co-packaged optics solution for accelerator chips to address scale-up networking for AI architectures.

Leading foundry TSMC has outlined its silicon photonics roadmap, which includes co-packaged optics.

And at the GTC 2025 AI developers conference, Nvidia announced it is adding co-packaged optics to its switch platforms for scale-out networking.

“All this is not a surprise because this is where we expected silicon photonics to be one day when we founded the company 10 years ago,” says Taha. “It is just that this day is happening now.”

Teramount sees its fibre attach product as a part of an emerging ecosystem to enable standard semiconductor high-volume manufacturing.

This ecosystem comprises chip designers, foundries, OSATs [outsourced semiconductor assembly and test service providers], and system integrators.

But there are challenges. There may be wafer-scale manufacturing, but issues remain on the integration-packaging side.

"This is why we need to travel, to align with the different partners," says Taha.

Challenges

Teramount is seeing challenges first-hand given its fibre-attach vantage point. Taha also highlights commercial issues still to be resolved.

The technical challenges revolve around integrating the silicon photonics die with the accompanying lasers and fibres in an advanced package.

Unlike a traditional pluggable optical transceiver, the silicon photonics chip is inserted in a hot environment and must meet operational temperatures of 85oC and even 105oC.

Multiple reflow soldering steps during manufacturing expose the packaging to even higher temperatures (270oC) and thermal stresses.

“These are new technical challenges that silicon photonic chip integration must meet 3D packaging requirements,” says Taha.

3D packaging has requirements that affect the fibre attach. For example, the silicon photonics chip is thinner than the die used in a pluggable if through-silicon via (TSV) technology is used.

TSV refers to the way a vertical electrical connector is done that passes through the die. Any mechanical stresses or warpage impacts the resulting optical performance of the die.

“Co-package optics is creating new challenges when connecting fibre to such thinner chips,” says Taha.

There are also issues with testing a design. “There are still no mature solutions for parallel optical and electrical testing,” says Taha.

The commercial issue he highlights centres around design ownership. With a pluggable module, all the components are delivered in one assembled device with one owner - the module maker.

With co-packaged optics, there are several stages of assembly, with components coming from multiple sources. “Who owns it?” says Taha.

Box system integrators making servers, switches, and the like don’t work with fibre. In contrast, co-packaged optics require connecting and managing hundreds of fibres that fit in a tight space. Good optical coupling and performance are a must to ensure the overall design.

“So this flow [for co-package optics] has yet to be set,” says Taha.

He says all the players, chip designers, foundry packaging vendors (OSATs), and system integrators still need to be aligned. That said, the industry, particularly the large silicon chip vendors, are working to make it happen, says Taha.

This implies that companies such as Nvidia, Intel, AMD, Broadcom, and Marvell are playing a key role here.

Given how the emerging AI opportunity is driving their chip businesses, they have every reason to make this work.