PCIe 3.0 and USB 3.0 to link mobile chip
Thursday, January 10, 2013 at 8:58AM - Both protocols to run on the MIPI Alliance's M-PHY transceiver
- Goal is to exploit existing PCIe and USB driver and application software while benefitting from the low power M-PHY
- OcuLink cable based on PCIe 3.0 promises up to 32 Gigabit
Source: Gazzetabyte
At first glance the Peripheral Component Interconnect Express (PCIe) bus has little in common with the Universal Serial Bus (USB) interface.
PCIe is a multi-lane bus standard used to move heavy data payloads over computing backplanes while USB is a consumer electronics interface. Yet certain areas of overlap are appearing.
The PCI Special Interest Group (PCI-SIG) is looking to get PCIe adopted within mobile devices - tablets and smartphones - for chip-to-chip communication, an application already performed by the 480Mbps USB 2.0 High-Speed Inter-Chip (HSIC) standard.
PCI-SIG is also developing the OcuLink external copper cable for storage and consumer applications.
PCIe is a point-to-point link that can also be switched, and is used to connect processors, processors to co-processors and for storage. Now, USB 3.0 and PCIe 3.0 are set to play an embedded role within mobile devices.
Handsets use the Mobile Industry Processor Interface (MIPI) Alliance's interfaces centred on the handset's mobile application processor, with several MIPI point-to-point interfaces defined to link to the handset's baseband processor, display and camera sensor.
Two physical (PHY) devices - D-PHY or the M-PHY - are used by MIPI. The M-PHY is the faster of the two (up to 5.8Git/s compared to the D-PHY's 1Gbit/s). It is the M-PHY transceiver that is used in links between the handset’s application processor to the radio, display and camera sensor. And it is the M-PHY that will run the USB 3.0-based SuperSpeed InterChip (SSIC) - the follow-on to HSIC - and PCIe 3.0.
The motivation is to benefit from the huge amount of software drivers and applications developed for USB and PCIe, while taking advantage of M-PHY's lower power consumption than the USB's or PCIe's own transceivers.
M-PHY runs at 1.25-1.45Gbps while two faster versions are in development: 2.5-2.9Gbps and up to 5.8Gbps.
A PHY adaptor layer, known as the PIPE 3.0-to-M-PHY bridge, translates the USB protocol onto M-PHY. The same strategy is being pursued by the PCI-SIG using a logical PHY to run PCIe 3.0 on M-PHY.
The PCI-SIG group hopes to have the PCIe 3.0 mobile specification completed in the first quarter of 2013.
Meanwhile, the OcuLink cable will initially be a copper cable interface designed as a compact, low cost interface that will support one, two and four lanes of PCIe 3.0. Two versions are planned: a passive and an active copper cable before a fibre-based version will be developed.
Uses of OcuLink will include connecting to storage devices and to audiovisual equipment.
A more detailed article on PCIe and USB for mobile will appear in an upcoming article for New Electronics
Reader Comments (1)
A nice summary of many mobile interface technologies in play (PCIe, USB3, MIPI D-PHY and M-PHY) and specifically the adaptation of PCIe and USB3 to the MIPI M-PHY. Please note that MIPI Gear 3 at 5.8Gbps can only support PCIe Gen 2 at 5Gbps/lane and not Gen 3 at 8Gbps/lane.