Opnext's multiplexer IC plays its part in 100Gbps trial

AT&T’s 100 Gigabit-per-second (Gbps) coherent trial between Louisiana and Florida detailed earlier this week was notable for several reasons. It included a mix of 10, 40 and 100Gbps wavelengths, Cisco Systems' newest IP core router, the CRS-3, and a 100Gbps line-side design from Opnext.

 

According to Andrew Schmitt, directing analyst of optical at Infonetics Research, what is significant about the 100Gbps AT&T trial is the real-time transmission; unlike previous 100Gbps trials no received data was block-captured and decoded offline.

Such real-time transmission required the use of Opnext’s 100Gbps coherent design comprising its silicon germanium (SiGe) multiplexer chip, announced in January, and an FPGA mock-up of the receiver circuitry.

"Several industry observers claim coherent detection is the most significant development since the advent of dense wavelength division multiplexing"

The multiplexer IC implements polarisation-multiplexing quadrature phase-shift keying (PM-QPSK) modulation (also known as dual-polarisation QPSK or DP-QPSK) at a line rate of up to 128Gbit/s, to accommodate advanced forward error correction (FEC) needed for 100Gbps transmission.

Yet despite the high speed electronics, the IC can be surface-mounted, simplifying packaging and assembly while reducing the cost of the 100Gbps transponder.

Why is the multiplexer IC important?

To enable the transition to 100Gbps optical transmission its economics needs to be improved. 100Gbps line-side MSA modules are needed to complement emerging IEEE 100 Gigabit Ethernet optical transceivers.

The Optical Internetworking Forum (OIF) backed by industry players have alighted on PM-QPSK as the chosen modulation approach for 100Gbps line-side interfaces. Operators such as AT&T and Verizon also back the technology for 100Gbps deployments.

Such industry recognition of coherent detection using PM-QPSK is based on the technological benefits already demonstrated at 40Gbps by Nortel. Indeed several industry observers claim coherent detection is the most significant development since the advent of dense wavelength division multiplexing (DWDM). While Verizon has stated that its next-generation links will be optimised for 100Gbps coherent transmission.

But developing 100Gbps technology is costly, which is why the OIF and operators are keen to focus the industry’s development R&D dollars on a single technological approach to avoid what has happened for 40Gbps transmission where four modulation schemes were developed and are still being deployed.

Opnext is the first company to detail a 100Gbps multiplexer chip. By operating at 128Gbit/s, the device supports the OIF’s 100Gbps ultra long haul DWDM Framework document yet the chip is packaged within a ball grid array to enable the use of surface-mount manufacturing on the printed circuit board. This avoids the expense and design complications associated with using radio frequency connectors.

The IC could also be used for 40Gbps PM-QPSK transponders. “We might have chosen CMOS [for a 40Gbps design] but there is no reason not to run it at a lower speed,” says Matt Traverso, senior manager, technical marketing at Opnext.

Method used

The multiplexer IC is manufactured using a 0.13 micron SiGe process. The in-house design has been developed by the engineering team Opnext acquired with the purchase of StrataLight.

Design work began a year ago. The resulting chip takes 10 channels, each at up to 11.3Gbit/s, and coverts the data to four 32Gbps channels that are then phase encoded. The multiplexer chip outputs are two polarisations, each comprising two 32Gbps I and Q data streams (see diagram). For a complete 100Gbps line-card diagram, showing the multiplexer IC, demultiplexer/ receiver ASIC that make up the line side and the client-side module, click here.

The input channel rate of 11.3Gbps is to support the Optical Transport Network (OTN) ODU-4 format while the 32Gbps per channel ensures that there is sufficient bit headroom for powerful forward error correction. It is the need to support 32Gbps data rates that required Opnext to use SiGe technology. “CMOS is good for 25 to 28Gbps rates; beyond that for good optical transport you need silicon germanium,” says Traverso.

The consensus however is that the industry will consolidate on CMOS for the multiplexer and demultiplexer/ receiver ICs. It could be that when Opnext defined its multiplexer design goals and timeline, CMOS was not an option.

How was the use of surface-mount technology (SMT) made possible? “The physical interface of the IC was designed based upon SMT packaging models to allow for sufficient margin in the jitter budget to achieve good transmission performance,” says Traverso.  “The goal is to match the impedance over frequency from the chip contact through the packaging to the printed circuit board.”

Opnext has not said which foundry it is using to make the chip. Hitachi and IBM are obvious candidates but given Opnext’s history, Hitachi is most likely.

What next?

For 100Gbps line side transmission both multiplexing and demultiplexing circuitry are required. Opnext has detailed the multiplexing circuitry only.

At 100Gbps, the receiver circuitry requires the inverse demultiplexer circuitry – decoding the PM-QPSK signal and recovering the original 100Gbps (10x10Gbps) data. But also required are very high-speed analogue-to-digital converters (ADCs) along with a computationally powerful digital signal processor (DSP).

The ADC and DSP are used to recover the signal, compensating for chromatic and polarisation mode dispersions experienced during transmission. Given the channel data rate is 32Gbps, it implies that the ADCs are operating at 64 Gsample/s. 

This is why developing such a chip is expensive and so technically challenging. “It requires finances, technical talent, significant optics expertise, integrated circuit knowledge, DSP design and ADC expertise,” says Traverso.

The reputed fee for developing such an ASIC is US $20m. Given there are at least four system vendors, Opnext, and two transponder/ chip players believed to be developing such an ASIC, this is a huge collective investment. But then the ASIC is where system vendors and transponder makers can differentiate their coherent-based products.

The ASIC also highlights the marked difference between Gigabit Ethernet (GbE) and line-side interfaces.

For 40 and 100GbE transceivers, interoperability between vendors’ transceivers is key. Long-haul connections, in contrast, tend to be proprietary.  The industry may have alighted on a common modulation approach but paramount is optical performance. The ASIC, and the DSP and FEC algorithms it executes, is how vendor differentiation is achieved.

At OFC/NFOEC 2010 later this month working 100Gbps PM-QPSK modules are not expected. But it is likely that Opnext and others will detail their 100Gbps demultiplexing/ receiver ASICs.  Meanwhile, coherent modules at 40Gbps are expected.

References

[1] “Performance of Dual-Polarization QPSK for Optical Transport Systems” by Kim Roberts et al, click here.