Microchip launches the first terabit physical layer device

Microchip Technology has unveiled a family of physical layer (PHY) Ethernet devices with a capacity of 1.2 terabits.

The Meta-DX1 PHY family comprises three devices that support three 400 Gigabit Ethernet (GbE) channels, a dozen 100GbE channels or 24, 10GbE channels. 

“We are not aware of any PHY in the industry that supports more than one terabit of traffic,” says Stephen Docking, manager, product marketing at the communications business unit of Microchip. 

Source: Microchip Technology

The company is also claiming another industry first in offering a PHY that supports the Open Internetworking Forum’s (OIF) Flexible Ethernet (FlexE) standard. 

We are not aware of any PHY in the industry that supports more than one terabit of traffic

Drivers

Two main factors are influencing the design of Ethernet PHY devices, says Microchip.  

One is the natural transition to new Ethernet rates that PHY designs must support. Such Ethernet rates bring their own requirements in terms of the serialiser-deserialiser (serdes) design and the forward-error correction scheme used.

The second driver of PHYs is the changing system requirements of router and switch platforms. Increasingly, functions are being offloaded from a packet processor or a switch ASIC and moved to the PHY.

Microchip’s Docking cites the example of MACsec encryption. “People want to see the traffic leaving the data centre encrypted,” he says. 

Incorporating MACsec functionality on a switch chip, for example, adds to the overall die size for a feature that may only be used on a portion of the ports. “This is where a PHY can add a lot of advantage by adding such features so that the switch silicon doesn't need to,” says Docking.

But offloading to add more functionality onto the PHY, when does it stop being a PHY and becomes something else?

“The Meta-DX1 represents a class of PHY that is going to be more and more common in future,” says Kevin So, senior manager, product marketing, communications business unit at Microchip.

Devices such as coherent DSPs and packet processors face a space-power challenge forcing designers to optimise the functions they aim to deliver, says So: “It is forcing a lot of potential capabilities out to an external device”.

The 16nm CMOS Meta-DX1 family comprises three devices that all support 1.2 terabits of capacity. 

The PM6110 supports all the PHY’s features, the PM6108 includes all the features but not FlexE, while the third device, the PM6104, is suited to applications that require neither FlexE nor MACsec. The PM6104 also doesn’t feature an Interlaken interface. 

Microchip has yet to reveal the order in which the family’s devices will be released.

FlexE  

The FlexE feature enables the bonding of Ethernet channels to achieve link speeds exceeding the faster Ethernet rate. The standard also allows for sub-links to be used, to send data over lower speed links for data transfer. The third attribute of FlexE is its support for non-standard Ethernet client rates.      

One reason why FlexE is needed is the advent of packet processors, used in routers, that support bandwidths far greater than 400GbE.  

Equally, the latest coherent DSPs that use probabilistic constellation shaping can support non-standard line rates in increments as small as 25 gigabits. “For such coherent processors, how do you get a signal to that DSP in 25-gigabit increments?” says Docking. 

Source: Microchip Technology

He cites an example of sending 275 gigabits over an optical link. By placing the FlexE-enabled Meta-DX1 on a switch or a router, the IC can mark some of the ‘calendar slots’ used in FlexE as unavailable. 

“This gives information to the coherent DSP that receives the signal that it may be 400 gigabits of bandwidth but it will see a bunch of unavailable calendar slots,” says Docking. “After these slots are dropped, it will up end up with 275 gigabits, the desired rate.”     

Docking says FlexE will first appear on routers used by the hyperscalers in their data centres. Telecom operators will follow soon after, adopting the technology in their networks.

The Meta-DX1 represents a class of PHY that is going to be more and more common in future

Additional features 

Other features the Meta-DX1 supports besides MACsec encryption include gearbox functionality that translates between 10 and 25 gigabits non-return-to-zero (NRZ), and between 25-gigabit NRZ and 56-gigabit 4-level pulse-amplitude modulation (PAM-4). 

Having the gearbox function on-chip allows a high-capacity switch chip that uses 56-gigabit PAM-4 signals to talk to a 100-gigabit QSFP28 optical module, for example.

The Meta-DX1 also supports the Precision Time Protocol (PTP) used to synchronise clocks across a network with high accuracy that is a requirement for 5G. 

The device family also features a hitless 2:1 multiplexer. The multiplexer function is suited for centralised switch platforms where the system intelligence resides on a central card while the connecting line cards are relatively simple, typically comprising a PHY and optical modules. 

In such systems, due to the central role of the switch card, a spare card is included in the platform. Should the primary card fail, the backup card kicks in, whereby all the switch’s line cards connect to the backup. By having a 2:1 multiplexer in the PHY, each line card can interface to both switch cards: the primary one and the backup.

“The challenge we are solving is not so much to switch, the key point is that we can do so hitlessly,” says Docking. “We can align the traffic and do the switchover such that the other end doesn't think the link has gone down and reroute the traffic.”

Lastly, the Meta-DX1 PHYs features what Microchip refers to as crosspoint serdes. It means that as equipment users upgrade the optics, say from a pluggable 100-gigabit QSFP28 to a 400-gigabit QSFP-DD, there are enough pins to connect the ASIC to the optics. The PHY acts as an intermediary between the ASIC and the optics, ensuring that there are enough pins whatever the mix of pluggables used. One linecard can thus be used whatever the mix of 100-gigabit and 400-gigabit QSFP optics. 

Microchip says samples of the Meta-DX1 are expected in the third quarter of this year.