How to shepherd a company’s technologies for growth
CTO interviews part 3: Dr Julie Eng
- Eng is four months into her new role as CTO of Coherent.
- Previously, she headed Finisar’s transceiver business and then the 3D sensing business, first at Finisar and then at II-VI. II-VI changed its name to Coherent in September 2022
- “CTO is one of these roles that has no universal definition,” says Eng
ulie Eng loved her previous role.
She had been heading II-VI’s (now Coherent’s) 3D sensing unit after being VP of engineering at Finisar’s transceiver business. II-VI bought Finisar in 2019.
She moved across to a new 3D sensing business while still at Finisar. The 3D sensing unit was like a start-up within a large company, she says.
II-VI and Finisar had been competitors in the 3D sensing market. Eng headed the combined units after Finisar’s acquisition.
She enjoyed the role and wasn’t looking to change when the CEO asked her to become Coherent’s CTO.
“To become CTO of the new Coherent – to help define the future of this company which is a five-plus going on six billion dollar company – that is pretty exciting,” says Eng.
The “New” Coherent
Coherent combines a broad portfolio of technologies from II-VI, Finisar, and the firm Coherent which II-VI acquired in 2022.
Just within lasers, Coherent’s portfolio spans from devices 1mm wide that are sold into mobile phones to the former Coherent’s lasers that are meters wide and used for OLED manufacturing.
Being CTO is different from Eng’s line-management roles, which had set, tangible annual goals.
Her role now is to shepherd the company’s technologies and grow the business over the long term.
Eng has been familiarising herself with the company’s technologies. To this aim, Eng is drawing on deep technological expertise across the company’s units.
Luckily, lasers are already covered, she quips.
“One of the things that I always somehow had a knack for is interacting with customers, sensing opportunities, and then figuring out how our technologies can help customers solve their problems,” says Eng.
It is a skill she successfully transferred to the consumer – 3D sensing – business but now it will be needed on a broader scale.
Eng is also making connections across technology units within the company as she seeks to identify new technologies and new market opportunities.
Her CTO role also allows her to engage with every Coherent customer across the company’s many markets.
She admits being CTO is challenging. One issue is grappling with the breadth of technologies the company has. Another is how to assess her works’ impact.
She and the CEO have discussed how best to use her time to benefit the company. Eng has also talked to other companies’ CTOs about the role and what works for them.
“It’s very interesting; CTO is one of these roles that has no universal definition,” says Eng.
Technologies to watch
Eng highlights several developments when asked about noteworthy technologies.
For communications, this is the year when 200 gigabits per lane will likely be achieved.
“The first transceivers I worked on were [SONET/SDH] OC-3 which is 155 megabits per second (Mbps),” she says. “Is wasn’t even a transceiver back then; it was discrete transmitters and receivers.”
That the industry has accelerated technology to achieve multiple lanes of 200 gigabit-per-second (Gbps) in a pluggable module is remarkable, she says.
Eng also notes Coherent’s work on a continuous-wave laser integrated with a Mach-Zehnder modulator – a DMZ – to enable 200 gigabits per lane.
The company is also active in life sciences and health monitoring. Communications, especially during the pandemic, showed its importance in people’s lives. “But life sciences and health-related products have a much more direct impact on people,” says Eng. “That is not something I’ve had direct exposure to.”
Life sciences and health monitoring is a segment where optics and optical devices will play a growing role over time.
Medical devices often originate in research environments such as hospital labs before becoming medical instruments. From the lab, they go to clinical. “What we are talking about here is going from lab to clinical to therapeutics,” she says.
The US Chips Act also heartens Eng: “It was about time for the US to prioritise semiconductors.”
Low-power coherent DSPs
Coherent and ADVA jointly developed a low-power coherent digital signal processor (DSP) and optics design for a 100-gigabit ZR (100ZR) design that fits within a QSFP28 module.
“We have an internal DSP team, and they are developing DSPs for the coherent optics market,” says Eng, adding that having the design team gives Coherent options.
Meanwhile, the debate about direct detection technology versus coherent optics continues.
As optical lane speed increases from 100 gigabits to 200 gigabits, the question remains what reach will direct detection achieve before running out of steam?
With 200 gigabits per lane, 800 gigabit modules can be achieved using four optical lanes, while for 1.6 terabits, eight lanes will be used.
Eng is confident that direct detection will support 10km at these speeds. Beyond 10km, direct detection becomes much more of a challenge, and coherent is an option.
“The real question is will coherent optics meet the size, cost and power consumption expectations of the data centre customers on a timeframe that meets their needs,” says Eng.
Having in-house DSP technology means Coherent can undertake design trade-offs and make the right decisions, she says.
After 1.6 terabits, the design options include increasing the lane rate, using more than eight channels or adopting more advanced modulation schemes.
“We look at the application, the timeline that the product needs to be released, the readiness of the technology, we do measurements – simulations – and we make objective decisions based on the results,” says Eng.
Whatever the prevalent technology is, says Eng, that technology will continue to improve since that is the livelihood of many companies.
“All of us, as an industry, are going to put our all into extending the technologies we currently have,” says Eng. So, when it comes to direct detection versus coherent, everyone will push direct detect technology as far as possible.
“Getting up to 1.6 terabits [using direct detect], that is pretty good,” says Eng. “That is going to last us a pretty long time.”
Materials
Coherent’s toolbox of material systems covers indium phosphide, silicon photonics, and gallium arsenide. It also has silicon carbide, a semiconductor suited for high-power transistors used for power electronics applications.
“We have all the technologies, we use the best technology for the product, and we use good engineering judgement,” says Eng.
Rather than favour indium phosphide or silicon photonics, Eng’s segmentation starts with whether the design is directly modulated or externally modulated.
Until now, up to 50 gigabits per lane has been well served by directly modulated lasers. This has used indium phosphide or, in the case of VCSELs, gallium arsenide.
“In general, directly modulated is the lower cost because the die is tiny, and often it is the lowest power,” says Eng.
But increasing the speed beyond 50Gbps gets more complicated with directly modulated lasers. This is where externally modulated lasers come in.
“Once you are already talking about an externally modulated solution, we start looking at the trade-offs between indium phosphide and silicon photonics,” says Eng.
The laser remains indium phosphide, so the bake-off concerns the modulator and the passive optics.
What indium phosphide brings is better electro-optics performance, while silicon photonics brings the benefits of integration.
“So if there is a high-lane count – lots of passives – or an opportunity to use one laser over multiple modulators, these can be complicated designs, and silicon photonics can help reduce the size,” says Eng.
Pluggables and co-packaged optics
With 200 gigabits per lane becoming available, there is a clear roadmap for 800-gigabits and 1.6-terabit pluggables.
“Customers like pluggables, and I don’t think people should underestimate that,” says Eng, adding that continued innovation will extend their lifetime.
“There are flyover cables between the switch ASIC and the modules, vertical line cards have been proposed, and we have shown board-mounted optical assemblies,” she says.
At some point, co-packaged optics may be the right solution, says Eng. But that will depend on the application’s specification, issues such as bandwidth, size, cost, power consumption and reliability.
“People will only transition to optical input-output when extending pluggables doesn’t make sense anymore,” says Eng. “I think it is probably five-plus years away, but there are probably error bars on that.”
Coherent’s activities include using indium phosphide manufacturing for external laser sources for co-package optics. “And we are working on silicon photonics,” she says.
Coherent is also working on co-packaging VCSELs with high-performance chips. “Not all applications require a 2km reach,” she says.
The coming decade’s opportunities
Eng’s thoughts about the growth opportunities for the coming decade are, not surprisingly, viewed through Coherent’s markets focus.
She highlights four segments: communications, industrial, instrumentation, and electronics.
Fibre-optics communications will continue to grow with bandwidth. The opportunities for innovation include datacom and coherent optics.
She also notes growing interest in free-space optics and satellite communications.
“I see money being spent on that and maybe that is a place where someone like ourselves, with a lot of optics as well as bigger lasers, can play a role,” says Eng.
Precision manufacturing uses lasers in the industrial segment. Eng cites cutting, welding and marking as examples.
“We have elements used for battery manufacturing which is increasing due to electric cars,” she says.
Excimer lasers are also used for OLED and microLED display manufacturing.
“We even have optics in extreme UV steppers [used for advanced process node chip manufacturing],” she says.
For instrumentation, much of the growth is around health life sciences. Coherent makes optics that are used inside PCR testers for COVID-19. It also has engineers working on solid state lasers used for flow cytometry (the sorting of cells). She also cites gene sequencing equipment and medical imaging.
Coherent’s electronics segment refers to the consumer market. Growth here for optics and lasers include AR/VR goggles and the metaverse, wearable health monitoring, and automotive.
For automotive, lasers are used for lidar and in-cabin sensing, such as driver and passenger monitoring.
Silicon carbide is also a growth market, and its uses include the wireless market and power devices for electric vehicles.
“I like the communications market, which we see as growing, but for us, with such a broad portfolio, there are many of these other markets and products that I see as exciting for the remainder of this decade,” says Eng.
Lumentum’s CTO discusses photonic trends
CTO interviews part 2: Brandon Collings
- The importance of moving to parallel channels will only increase given the continual growth in bandwidth.
- Lumentum’s integration of NeoPhotonics’ engineers and products has been completed.
- The use of coherent techniques continues to grow, which is why Lumentum acquired the telecom transmission product lines and staff of IPG Photonics.
“It has changed quite significantly given what Lumentum is engaging in,” he says. “My role spans the entire company; I’m engaged in a lot of areas well beyond communications.”
A decade ago, the main focus was telecom and datacom. Now Lumentum also addresses commercial lasers, 3D sensing, and, increasingly, automotive lidar.
Acquisitions
Lumentum was busy acquiring in 2022. The deal to buy NeoPhotonics closed last August. The month of August was also when Lumentum acquired IPG Photonics’ telecom transmission product lines, including its coherent digital signal processing (DSP) team.
NeoPhotonics’ narrow-linewidth tunable lasers complement Lumentum’s modulators and access tunable modules. Meanwhile, the two companies’ engineering teams and portfolios have now been merged.
NeoPhotonics was active in automotive lidar, but Lumentum stresses it has been tackling the market for several years.
“It’s an area with lots of nuances as to how it is going to be adopted: where, how fast and the cost dependences,” says Collings. “We have been supplying illuminators, VCSELs, narrow-linewidth lasers and other technologies into lidar solutions for several different companies.”
Lumentum gained a series of technological capabilities and some products with the IPG acquisition. “The big part was the DSP capability,” says Collings.
ROADMs
Telecom operators have been assessing IP-over-DWDM anew with the advent of coherent optical modules that plug directly into an IP router.
Cisco’s routed optical networking approach argues the economics of using routers and the IP layer for traffic steering rather than at the optical layer using reconfigurable optical add-drop multiplexers (ROADMs).
Is Lumentum, a leading ROADM technology supplier, seeing such a change?
“I don’t think there is a sea change on the horizon of moving from optical to electrical switching,” says Collings. “The reason is still the same: transceivers are still more expensive than optical switches.”
That balance of when to switch traffic optically or electrically remains at play. Since IP traffic continues to grow, forcing a corresponding increase in signalling speed, savings remain using the optical domain.
“There will, of course, be IP routers in networks but will they take over ROADMs?” says Collings. “It doesn’t seem to be on the horizon because of this growth.”
Meanwhile, the transition to more flexible optical networking using colourless, directionless, contentionless (CDC) ROADMs, is essentially complete.
Lumentum undertook four generations of switch platform design in the last decade to enable CDC-ROADM architectures that are now dominant, says Collings.
Lumentum moved from a simple add-drop to a route-and-select and a colourless, contentionless architecture.
A significant development was Lumentum’s adoption of liquid-crystal-on-silicon (LCOS) technology that enabled twin wavelength-selective switches (WSSes) per node that adds flexibility. LCOS also has enabled a flexible grid which Lumentum knew would be needed.
“We’re increasingly using MEMS technology alongside LCOS to do more complex switching functions embedded in colourless, directionless and contentionless networks today,” says Collings.
Shannon’s limit
If the last decade has been about enabling multiplexing and demultiplexing flexibility, the next challenge will be dealing with Shannon’s limit.
“We can’t stuff much more information into a single optical fibre – or that bit of the amplified spectrum of the optical fibre – and go the same distance,” says Collings. “We’ve sort of tapped out or reached that capacity.”
Adding more capacity requires amplified fibre bandwidth, such as using the L-band alongside the C-band or adding a second fibre.
Enabling such expansion in a cost- and power-efficient way will be fundamental, says Collings, and will define the next generation of optical networks.
Moreover, he expects consumer demand for bandwidth growth to continue. More sensing and more up-hauling of data to the cloud for processing will occur.
Accordingly, optical transceivers will continue to develop over the next decade.
“They are the complement requirement for scaling bandwidth, cost and power effectively,” he says.
Parallelism
Continual growth of bandwidth over the next decade will cause the industry to experience technological ceilings that will drive more parallelism in communications.
“If you look in data centres and datacom interconnects, they have long moved to parallel interface implementations because they felt that bandwidth ceiling from a technological, power dissipation or economic reason.”
Coherent systems have a symbol rate of 128 gigabaud (GBd), and the industry is working on 256GBd systems. Sooner or later, the consensus will be that the symbol rate is fast enough, and it is time to move to a parallel regime.
“In large-scale networks, parallelism is going to be the new thing over the next ten years,” says Collings.
Coherent technology
Collings segments the coherent optical market into three.
There are high-end coherent designs for long-haul transport developed by optical transport vendors such as Ciena, Cisco, Huawei, Infinera and Nokia.
Then there are designs such as 400ZR developed for data centre interconnect. Here a ‘pretty aggressive’ capability is needed but not full-scale performance.
At the lower end, there are application areas where direct-detect optics is reaching its limit. For example, inside the data centre, campus networks and access networks. Here the right solution is coherent or a ‘coherent-light’ technology that is a compromise between direct detection and full-scale coherence used for the long haul.
“So there is emerging this wide continuum of applications that need an equal continuum of coherent technology,” says Collings.
Now that Lumentum has a DSP capability with the IPG acquisition, it can engage with those applications that need solutions that use coherent but may not need the highest-end performance.
800 gigabits and 1.6 terabits
There is also an ongoing debate about the role of coherent for 800-gigabit and 1.6-terabit transceivers, and Collings says the issues remain unclear.
There’s a range of application requirements: 500m, 2km, and 10km. A direct-detect design may meet the 500m application but struggle at 2k and break down at 10km. “There’s a grey area, just in this simple example,” he says.
Also, the introduction of coherent should be nuanced; what is not needed is a long-haul 5,000km DSP. It is more a coherent-light solution or a borrowing from coherent technologies, says Collings: “You’re still trying to solve a problem that you can almost do with direct detect but not quite.”
The aim is to use the minimum needed to accomplish the goal because the design must avoid paying the cost and power to implement the full complement coherent long-haul.
“So that’s the other part of the grey area: how much you borrow?” he says. “And how much do you need to borrow if you’re dealing with 10km versus 2km, or 800 gigabits versus 1.6 terabits.”
Data centres are already using parallel solutions, so there is always the option to double a design through parallelism.
“Eight hundred gigabit could be the baseline with twice as many lanes as whatever we’re doing at 400 gigabits,” he says. “There is always this brute force approach that you need to best if you’re going to bring in new technologies.”
Optical interconnect
Another area Lumentum is active is addressing the issues of artificial intelligence machine-learning clusters. The machine-learning architectures used must scale at an unprecedented rate and use parallelism in processors, multiple such processors per cluster, and multiple clusters.
Scaling processors requires the scaling of their interconnect. This is driving a shift from copper to optics due to the bandwidth growth involved and the distances: 100, 200 and 400 gigabits and lengths of 30-50 meters, respectively.
The transition to an integrated optical interconnect capability will include VCSELs, co-packaged optics, and much denser optical connectivity to connect the graphic processing units (GPUs) rather than architectures based on pluggables that the industry is so familiar with, says Collings.
Co-packaged optics address a power dissipation interconnect challenge and will likely first be used for proprietary interconnect in very high density GPU artificial intelligence clusters.
Meanwhile, pluggable optics will continue to be used with Ethernet switches. The technology is mature and addresses the needs for at least two more generations.
“There’s an expectation that it’s not if but when the switchover happens to co-packaged optics and the Ethernet switch,” says Collings.
Material systems
Lumentum has expertise in several material systems, including indium phosphide, silicon photonics and gallium arsenide.
All these materials have strengths and weaknesses, he says.
Indium phosphide has bandwidth advantages and is best for light generation. Silicon is largely athermal, highly parallelisable and scalable. Staff joining from NeoPhotonics and IPG have strengthened Lumentum’s silicon photonics expertise.
“The question isn’t silicon photonics or indium phosphide. It’s how you get the best out of both material systems, sometimes in the same device,” says Collings. “Sticking in one sandbox is not going to be as competitive as being agile and having the ability to bring those sandboxes together.”
Former Compass Networks staff look to silicon photonics
The Compass Networks team that designed a novel chip with optical input-output is exploring new opportunities now that the IP core router venture has closed it doors.
The team plans to develop chips using silicon photonics for input-output and is involved in a European Commission (EC) Horizon 2020 project dubbed L3Matrix that will make such a chip for the data centre.
Kobi HasharoniCompass Network was the first company to sell a commercial product - an IP core router - that used an ASIC co-packaged with optics. The IP router was sold to several leading service providers including NTT Communications and Comcast but the venture ultimately failed.
Compass Networks has now become a software company, while its chip R&D team decided to spin off to keep the co-packaged IC and photonics technology alive.
Compass Networks
The ambitious Israeli start-up, Compass Networks, developed its IP core router to compete with the likes of Cisco Systems, Juniper Networks, Alcatel-Lucent (now Nokia) and Chinese giant, Huawei.
Using the chip - a traffic manager with optical input-output - resulted in a smaller, lower-power IP core router design. However, despite the compact platform enabled by the chip, the company failed commercially. The main issue was not the router hardware but the size of Compass Networks’ software team: its 60 engineers could not compete with its much larger IP core router rivals, says Kobi Hasharoni, who was director of electro-optics at Compass Networks.
An IP router takes traffic in the form of packets on its input ports and forwards them to their destination via its output ports. To do this, two functions are used: a network processor unit and a traffic manager. The two functions can be integrated in a single chip or, typically for core routers, implemented using two devices.
The network processor chip performs the packet processing, taking each packet’s header and using a look-up routing table to update the header with the destination address before sending the packet on its way.
The second chip, the traffic manager, oversees billions of packets. The chip implements the queueing protocols and, based on a set of rules, determines which packets have priority on what ports. In a conventional IP router there is also a switch fabric which connects the router cards to be able to send the packets to the required output port.
Compass Networks designed the router between 2007 and 2010. The design team chose the EZchip 100-gigabit NP-4 network processor for the router but developed its own complex traffic manager ASIC, adding the twist of optics for the chip’s input-output.
We didn’t have a backplane; our backplane was just fibres
The resulting chip - referred to as icPhotonics or the D-chip - performed the roles of both traffic manager and switch fabric.
Instead of the traffic manager going through switch fabrics chips and an electrical backplane to a traffic manager on another card, each traffic manager had sufficient bandwidth due to the optics to connect to all the other traffic managers in a mesh configuration.
“We didn’t have a backplane,” says Hasharoni. “Our backplane was just fibres.” Avoiding a backplane resulted in a more compact, lower-power IP core router that saved on operational costs.
D-chip
To make the D-chip, Compass developed a mixed signal ASIC. The 21x21 mm chip comprised the traffic manager and a matrix of analogue circuitry to interface to the optics.
The company used 168 vertical-cavity surface-emitting lasers (VCSELs) and 168 photo-detectors in a 2D array that was positioned above the analogue circuitry; each optical device positioned above its own analogue driver or receiver circuitry. Two ribbon cables, one for the VCSELs and one for the photo-detectors, were then connected to the chip.
VCSELs were at 10 gigabit-per-second (Gbps) at the time and Compass Networks chose to operate them at 8Gbps. “Going to 8 gigabit-per-second seemed reasonable,” says Hasharoni.
Each NP-4 processed 100Gbps of traffic and sent out 160Gbps to the D-chip. The extra traffic included forward error correction and overhead bits to speed up queueing.
The core router platform comprised four line cards, each card having two 100-gigabit NP-4s and two D-chips.
The total optical input-output bandwidth of each D-chip was 1.34 terabits in each direction. The 168 VCSELs were used in such a way that each group of 20 VCSELs supported the 160-gigabit stream of packets, enabling each D-chip to connect directly to the seven other D-chips in a fully connected mesh, while the 28 remaining VCSELs were used for redundancy.
At some point you will not get all this input-output into the ASIC
Silicon photonics
Were the team to tackle a similar design today, the designers would use silicon photonics instead of VCSELs, says Hasharoni. A silicon photonics design would support single-mode fibre and its associated longer reach, while the co-packaging would be easier given both the ASIC and the optics are silicon-based.
Hasharoni points to the rapid development in the capacity of switch chips used in the data centre. Current Ethernet switch silicon from the likes of Broadcom support 3.2 terabits of capacity and this will double in 2017 and double again to 12.8 terabits in 2018. There is even talk of 25.6 terabits switching silicon by 2020.
The issue, however, is that the input-output required for these higher-capacity chips consume more and more power; at 12.8 terabits it will be over half of chip's overall power consumption. "At some point you will not get all this input-output into the ASIC," says Hasharoni.
Using a co-packaged electronics and silicon photonics design, the input-output's power consumption will be halved, says Hasharoni. The optical density is also an order of magnitude higher, thus only a fraction of the ASIC area is used for chip input-output compared to conventional electrical input-ouput. And the resulting switch will not need optical transceivers. "The fibre goes out directly from the IC; the power saving is huge," says Hasharoni.
The EC Horizon 2020 L3Matrix project also includes IBM Research, the Fraunhofer Institute for Reliability and Microintergration (Fraunhofer IZM) and several universities. The project will use embedded III-V light sources on a silicon substrate along with optical modulators. The aim of the design is to develop low-latency, high-radix switch elements using 25Gbps single-mode fibres and waveguides.
"The novel thing here is the use of two-dimensional silicon photonics matrices on an ASIC," says Hasharoni.
Heterogeneous integration comes of age
Silicon photonics luminaries series
Interview 7: Professor John Bowers
August has been a notable month for John Bowers.
Juniper Networks announced its intention to acquire Aurrion, the US silicon photonics start-up that Bowers co-founded with Alexander Fang. And Intel, a company Bowers worked with on a hybrid integration laser-bonding technique, unveiled its first 100-gigabit silicon photonics transceivers.
Professor John BowersBower, a professor in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara (UCSB), first started working in photonics in 1981 while at AT&T Bell Labs.
When he became interested in silicon photonics, it still lacked a good modulator and laser. "If you don't have a laser and a modulator, or a directly modulated laser, it is not a very interesting chip,” says Bowers. "So I started thinking how to do that."
Bowers contacted Mario Paniccia, who headed Intel’s silicon photonics programme at the time, and said: “What if we can integrate a laser? I think there is a good way to do it.” The resulting approach, known as heterogeneous integration, is one that both Intel and Aurrion embraced and since developed.
This is a key Bowers trait, says Aurrion co-founder, Fang: he just knows what problems to work on.
"John came up with the concept of the hybrid laser very early on," says Fang. "Recall that, at that time, silicon photonics was viewed as nothing more than people making plasma-effect phase shifters and simple passive devices. John just cut to the chase and went after combining III-V materials with silicon."
If you look at the major companies with strong photonics activities, you’ll find a leader in that group that was developed under John’s training
Fang also highlights Bowers' management skills. “John can pick players and run teams,” says Fang, who describes himself as one of those privileged to graduate out of Bowers’ research group at UCSB.
“You find yourself in an environment where John picks a team of sharp folk with complementary skills and domain expertise to solve a problem that John determines as important and has some insight on how to solve it,” says Fang. “If we look like we are going to drive off the road, he nudges with a good mix of insight, fear, and humour.”
It has resulted in some of the best trained independent thinkers and leaders in the industry, says Fang: “If you look at the major companies with strong photonics activities, you’ll find a leader in that group that was developed under John’s training”.
Silicon photonics
Bowers defines silicon photonics as photonic devices on a silicon substrate fabricated in a CMOS facility.
“Silicon photonics is not about using silicon for everything; that misses the point,” says Bowers. “The key element is using silicon as a substrate - 12-inch wafers and not 2- or 3-inch wafers - and having all the process capability a modern silicon CMOS facility brings.” These capabilities include not just wafer processing but also advanced testing and packaging.
The world is about to change and I don't think people have quite figured that out
“If you go to an advanced packaging house, they don't do 6-inch wafers and I don't know of indium phosphide and gallium arsenide wafers larger than 6 inches,” says Bowers. “The only solution is to go to silicon; that is the revolution that hasn't happened yet but it is happening now.”
Bowers adds that everything Aurrion does, there is automated test along the way. "And I think you have others; Luxtera has done a great job as well at wafer-level test and packaging," he says. "The world is about to change and I don't think people have quite figured that out."
Working with Intel was an eye-opener for Bowers, especially the process controls it applies to chip-making.
“They worry about distributions and yields, and it is clear why there are seven billion transistors on a chip and that chip will yield,” says Bowers. “When you apply that to photonics, it will take it to a whole new level.” Indeed, Bowers foresees photonics transfering to silicon.
Bowers highlights the fairly complex chips now being developed using silicon photonics.
“We have done a 2D scanner - a 32-element phased array - something one could never do in optics unless it was integrated all on one chip,” he says. The phased-array chip comprises 160 elements and is physically quite large.
This is another benefit of using 12-inch silicon wafers and fabricating the circuits in a CMOS facility. “You are not going to cost-effectively do that in indium phosphide, which I've worked on for the last 30 years,” says Bowers.
Another complex device developed at UCSB is a 2.54-terabit network-on-a-chip. “This is a larger capacity than anyone has done on any substrate,” he says.
Infinera’s latest photonic integrated circuit (PIC), for example, has a transport capacity of up to 2.4 terabit-per-second. That said, Bowers stresses that the network-on-a-chip is a research presentation while Infinera’s PIC is a commercial device.
Heterogeneous integration
Heterogeneous integration involves bonding materials such as III-V compounds onto silicon.
Bowers first worked on III-V bonding with HP to make longer wavelength - 1310nm and 1550nm - VCSELs. “We had been bonding indium phosphide and gallium arsenide to solve a fundamental problem that indium phosphide does not make good mirrors,” he says. “So I was pretty confident we could bond III-V to silicon to add gain to silicon photonics to then add all the laser capability.”
Bonding to silicon is attractive as it enables the integration of optical features that haven't been widely integrated onto any other platform, says Bowers. These include not only lasers but other active devices such as modulators and photo-detectors, as well as passive functions such as isolators and circulators.
One concern raised about heterogeneous integration and the use of III-V materials is the risk of contamination of a CMOS fabrication line.
Bowers points out that the approached used does not impact the front end of the fabrication, where silicon wafers are etched and waveguides formed. The III-V material is bonded to the wafer at the fab’s back end, the stage where metallisation occurs when making a CMOS chip.
The leading chipmakers are also experimenting with III-V materials to create faster digital devices due to their higher electron mobility. “This is part of the natural evolution of CMOS,” he says. It remains unclear if this will be adopted, but it is possible that a 5nm CMOS node will use indium phosphide.
“All the CMOS houses are doing lots of work on III-V and silicon,” says Bowers. “They have figured out how to control that contamination issue.”
New capabilities
Bowers and his team have already demonstrated the integration of new optical functions on silicon.
“Neither silicon nor indium phosphide has an isolator and one always has to use an external YIG (yttrium iron garnet) isolator to reduce the reflection sensitivity of things like widely tunable lasers,” says Bower.
His team has developed a way to bond a YIG onto silicon using the same techniques it uses for bonding III-V materials. The result is an integrated isolator device with 32dB isolation and a 2dB insertion loss, a level of performance matching those of discrete isolators.
Incorporating such functionality onto silicon creates new possibilities. “We have a paper coming out that features a 6-port circulator,” says Bowers. “It is not a tool that the community can use yet because it has never been made before but we can do that on silicon now,” he says. “That is a good new capability.”
Superior performance
Bowers stresses that heterogeneous integration can also result in optical performance superior to a III-V design alone. He cites as an example how using a silicon nitride waveguide, with its lower loss that indium phosphide or gallium arsenide, can create high-quality Q-resonators.
A Q-resonator can be viewed as a form of filter. Bowers' group have demonstrated one with a Q of 80 million. “That makes it very sensitive to a variety of things,” he says. One example is for sensors, using a Q resonator with a laser and detector to form a spectrometer.
His researchers have also integrated the Q resonator with a laser to make a widely tunable device that has a very narrow line-width: some 40kHz wide. This is a narrower than the line-width of commercially-available tunable lasers and exceeds what can be done with indium phosphide alone, he says.
Challenges
Bowers, like other silicon photonics luminaries, highlights the issues of automated packaging and automated testing, as important challenges facing silicon photonics. “Taking 10,000s of transceivers and bringing all the advanced technology - not just processing but test and packaging - that are being developed for cell phones,” he says.
Too much of photonics today is based on gold boxes and expensive transceivers. “Where Aurrion and Intel are going is getting silicon photonics to the point where photonics will be ubiquitous, cheap and high yielding,” he says. This trend is even evident with his university work. The 400-element 2.54-terabit network-on-a-chip has very high laser yields, as are its passive yields, he says.
“So, effectively, what silicon photonics can do is going up very rapidly,“ says Bowers. “If you can put it in the hands of a real CMOS player like Intel or the companies that Aurrion uses, it is going to take photonics to a whole new area that people would not have thought possible in terms of complexity.”
Yet Bowers is also pragmatic. “It still takes time,” he says. “You can demonstrate an idea, but it takes time to make it viable commercially.”
He points to the recently announced switch from Oracle that uses mid-board optics. “That is a commercial product out there now,” he says. “But is it silicon photonics? No, it is VCSEL-based; that is the battle going on now.”
VCSELs have won the initial battle in the data centre but the amount of integration the technology can support is limited. Once designers move to wavelength-division multiplexing to get to higher capacities, where planar technology is required to combine and separate the different wavelengths efficiently, that is when silicon has an advantage, he says.
The battle at 100 gigabit between VCSELs and silicon photonics is also one that Bowers believes silicon photonics will eventually win. But at 400 gigabit and one terabit, there is no way to do that using VCSELs, he says.
Status
The real win for silicon photonics is when optics moves from transceivers at the edge of the board to mid-board and eventually are integrated with a chip in the same package, he says.
Advanced chips such as switch silicon for the data centre are running into an input-output problem. There are only so many 25 gigabit-per-second signals a chip can support. Each signal, sent down a trace on a printed circuit board, typically requires equalisation circuitry at each end and that consumes power.
Most of the photonics industry has focused on telecom and datacom, and justifiably so. The next big thing will happen in the area of sensors.
A large IC packaged as a ball grid array may have as many as 5,000 bumps (balls) that are interfaced to the printed circuit board. Using photonics can boost the overall bandwidth coming on and off the chip.
“With photonics, and in particular when we integrate the laser as well as the modulator, the world doesn't see it as a photonics chip, it's an electronics chip, it just turns out that some of those bumps are optical ones and they provide much more efficient transmission of data and at much lower power,” say Bowers. A 100 terabit of even a 1000 terabit - a petabit - switch chip then becomes possible. This is not possible electrically but it is possible by integrating photonics inside the package or on the chip itself, he says.
“That is the big win eventually and that is where we help electronics extend Moore’s law,” says Bowers.
And as silicon photonics matures, other applications will emerge - More than Moore’s law - like the use of photonics for sensors.
“Most of the photonics industry has focused on telecom and datacom, and justifiably so,” says Bowers. “The next big thing will happen in the area of sensors.”
Professor Bowers was interviewed before the Juniper Networks announcement
Intel's 100-gigabit silicon photonics move
Intel has unveiled two 100-gigabit optical modules for the data centre made using silicon photonics technology.
Alexis Bjorlin
The PSM4 and CWDM4/CLR4 100-gigabit modules mark the first commercial application of a hybrid integration technique for silicon photonics, dubbed heterogeneous integration, that Intel has been developing for years.
Intel's 100-gigabit module announcement follows the news that Juniper Networks has entered into an agreement to acquire start-up, Aurrion, for $165 million. Aurrion is another silicon photonics player developing this hybrid integration technology for its products.
Hybrid integration
With heterogeneous integration, materials such as indium phosphide and gallium arsenide can be bonded to the silicon substrate before the 300mm wafer is processed to produce the optical circuit. Not only can lasers be added to silicon but other active devices such as modulators and photo-detectors as well as passive functions such as isolators and circulators.
There is no alignment needed; we align the laser with lithography
Intel is using the technique to integrate the laser as part of the 100-gigabit transceiver designs.
"Once we apply the light-emitting material down to the silicon base wafer, we define the laser in silicon," says Alexis Bjorlin, vice president and general manager, Intel Connectivity Group. “There is no alignment needed; we align the laser with lithography.”
Intel claims it gets the highest coupling efficiency between the laser and the optical waveguide and modulator because it is lithographically defined and requires no further alignment.
100-gigabit modules
Intel is already delivering the 100-gigabit PSM4 module. “First volume shipments are happening now,” says Bjorlin. Microsoft is one Internet content provider that is using Intel’s PSM4.
The chip company is also sampling a 100-gigabit CWDM4 module that also meets the more demanding CLR4 Alliance’s optical specification. The 100-gigabit CLR4 module can be used without forward-error correction hardware and is favoured for applications where latency is an issue such as high-performance computing.
Intel is not the first vendor to offer PSM4 modules, nor is it the first to use silicon photonics for such modules. Luxtera and Lumentum are shipping silicon photonics-based PSM4 modules, while STMicroelectronics is already supplying its PSM4 optical engine chip.
We are right on the cusp of the real 100-gigabit connectivity deployments
“Other vendors have been shipping PSM4 modules for years, including large quantities at 40 gigabit,” says Dale Murray, principal analyst at LightCounting Market Research. “Luxtera has the clear lead in silicon photonics-based PSM4 modules but a number of others are shipping them based on conventional optics.”
The PSM4 is implemented using four independent 25-gigabit channels sent over a single-mode ribbon fibre. Four fibres are used for transmission and four fibres for receive.
“The PSM4 configuration is an interesting design that allows one laser to be shared among four separate output fibres,” says Murray. “As Luxtera has shown, it is an effective and efficient way to make use of silicon photonics technology.”
The CWDM4 is also a 4x25-gigabit design but uses wavelength-division multiplexing and hence a single-mode fibre pair. The CWDM4 is a more complex design in that an optical multiplexer and demultiplexer are required and the four lasers operate at different wavelengths.
“While the PSM4 module does not break new ground, Intel’s implementation of WDM via silicon photonics in a CWDM4/CLR4 module could be more interesting in a low-cost QSFP28 module,” says Murray. WDM-based QSFP28 modules are shipping from a number of suppliers that are using conventional optics, he says.
Intel is yet to detail when it will start shipping the CWDM4/CLR4 module.
Market demand
Bjorlin says the PSM4 and the CWDM4/CLR4 will play a role in the data centre. There are applications where being able to break out 100-gigabit into 25-gigabit signals as offered by the PSM4 is useful, while other data centre operators prefer a duplex design due to the efficient use of fibre.
“We are right on the cusp of the real 100-gigabit connectivity deployments,” she says.
As for demand, Bjorlin expects equal demand for the two module types in the early phases: “Longer term, we will probably see more demand for the duplex solution”.
LightCounting says that 100-gigabit PSM4 modules took an early lead in the rollout of 100 Gigabit Ethernet, with VCSEL-based modules not far behind.
“Some are shipping CWDM4/CLR4 and we expect that market to ramp,” says Murray. “Microsoft and Amazon Web Services seem to like PSM4 modules while others want to stick with modules that can use duplex fibre.
Source: Intel
Data centre switching
“One of the most compelling reasons to drive silicon photonics in the future is that it is an integratable platform,” says Bjorlin.
Switch silicon from the likes of Broadcom support 3.2 terabits of capacity but this will increase to 6.4 terabits by next year and 12.8 terabits using 4-level pulse amplitude modulation (PAM-4) signalling by 2018 (see chart). And by 2020, 25.6-terabit capacity switch chips are expected.
The demand for 100 gigabit is for pluggable modules that fit into the front panels of data center switches. But the market is evolving to 400-gigabit embedded optics that sit on the line card, she says, to enable these emerging higher-capacity switches. Intel is a member of the Consortium of On-Board Optics (COBO) initiative that is being led by Microsoft.
“When you get to 25.6-terabit switches, you start to have a real problem getting the electrical signals in and out of the switch chip,” says Bjorlin. This is where silicon photonics can play a role in the future by co-packaging the optics alongside the switch silicon.
“There will be a need for an integrated solution that affords the best power consumption, the best bandwidth-density that we can get and effectively position silicon photonics for optical I/O [input/output],” says Bjorlin. “Ultimately, that co-packaging is inevitable.”
The ecosystem for silicon photonics starts to take shape
Silicon photonics luminaries series
Interview 6: imec - Philippe Absil and Joris Van Campenhout
Imec has a unique vantage point when it comes to the status and direction of silicon photonics.
The Belgium nano-electronics research centre gets to see prototype designs nearing commercialisation due to its silicon photonics integration platform and foundry service. “We allow companies to build prototypes using a robust silicon photonics technology,” says Philippe Absil, department director for 3D and optical technologies at imec.
Philippe Absil
Imec also works intimately with several partners on longer-term research, one being Huawei. This optical I/O R&D activity is part of imec’s CORE CMOS scaling R&D programme which as well as Huawei includes GlobalFoundries, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony and TSMC. The research is sufficiently far ahead to be deemed pre-competitive such that all the firms collaborate.
For silicon photonics, the optical I/O research includes optical integration schemes, new device concepts and new materials. “The aim is to bring silicon photonics technology to the next level in order to resolve today’s challenges,” says Absil.
Assured future
Imec is confident about silicon photonics’ future but stresses an ecosystem for the technology needs to be in place first. This means having more than one foundry, suitable equipment to reduce the cost of testing silicon photonics circuits, and developing packaging solutions.
“These elements are being developed and the ecosystem is coming together nicely,” says Joris Van Campenhout, programme director for optical I/O at imec.
Another encouraging sign is the strong industry interest in the technology in the last two years. It was mainly academics that were interested in imec's multi-wafer project service but now there is strong demand from companies as well; companies bringing products to market.
Silicon photonics is not a one-off technology; it has value for several generations
Systems scaling is what gives imec confidence that silicon photonics will not end up a niche technology. “Look at the cloud economy and cloud data centres, these systems need to scale continually,” says Van Campenhout. “A lot of effort is being put into scaling, and interconnect is an essential part of such systems.”
Moreover, there are few technologies to deliver such scalability, which is why many of the bigger systems companies are investing in silicon photonics. “Silicon photonics is not a one-off technology; it has value for several generations," says Van Campenhout. “That is really the potential of silicon photonics and that is where the disruption lies.”
Challenges
One focus for imec and its partners is to reduce the overall insertion loss of silicon photonics circuits for short-reach interconnect applications. Such short-reach links span distances of up to a few meters, a market segment currently addressed using advanced copper cabling or VCSEL-based optical interconnects.
Joris Van Campenhout
Because of the relatively high insertion loss of silicon photonics designs, it is not possible to achieve a sufficiently low-power consumption for such links. “That is a show-stopper because it prevents us closing link budgets,” says Van Campenhout. A link budget refers to the gain and losses across the elements making up the optical link such as the laser, modulator, optical fibre and receiver circuitry.
In order to drive up volumes, silicon photonics needs to become more competitive at shorter reaches where VCSELs are still the mainstream optical technology
The team is tackling the loss issue on two fronts: reducing the insertion loss between the fibre and the waveguide, and reducing the modulator's insertion loss which still exceeds that of other optical technologies.
“For these two parts of the technology, further improvements are required to reduce the overall losses,” says Van Campenhout. “That will enable us to be competitive at shorter distances.” These are engineering challenges, he stresses, rather than any fundamental problem.
Another silicon photonics research area being explored at imec include edge coupling solutions between the waveguide and fibre. “These can have very low insertions losses - one decibel or lower - and can be polarisation insensitive," says Van Campenhout.
Packaging approaches that have a low insertion loss are also being developed, engineered in a way to enable passive alignment assembly procedures. Passively aligning the laser is a key part of reducing component packaging costs. “Silicon doesn’t have a laser so in the next few years it will continue to require hybrid solutions,” says Van Campenhout. “You need a good way to do passive alignment of laser sources, and also packaged in a way that doesn’t require a hermetic solution.”
These are the challenges facing the industry in the next few years: lowering insertion loss and developing packaging technologies. Overcoming these challenges will mark an important milestone since the total market for silicon photonics can be served with a small number of silicon wafers. “In order to drive up volumes, silicon photonics needs to become more competitive at shorter reaches where VCSELs are still the mainstream optical technology,” says Van Campenhout.
It is not yet mature but there is a broader adoption of a model whereby silicon photonics can be designed by one company and fabricated by another
Value proposition
Overall, silicon photonics faces stiff competition from VCSELs and indium phosphide. The two established optical technologies continue to evolve and benefit from having all the optical functionality in one platform, something that silicon photonics, with its lack of a laser source, can’t match.
But the trend whereby the optical transceiver is coming ever closer to the host IC strengthens silicon photonics’ hand. That is because silicon photonics can be co-packaged with silicon, and can share the same equipment as the two device types - electronic and photonic ICs - are put together.
Absil also highlights how the ecosystem needed for widespread adoption of silicon photonics is taking shape. “It is not yet mature but there is a broader adoption of a model whereby silicon photonics can be designed by one company and fabricated by another,” he says. “The adoption of that will result in a new model for the optical component world.”
Market opportunities
Van Campenhout expects silicon photonics to be a niche technology for 100-gigabit connections in the data centre. This may change as silicon photonics matures but today the market is dominated by III-V technologies, he says.
Applications that require integration density in the form of a large number of parallel high-speed transceivers, and close integration with host ICs is what will drive silicon photonics. Imec cites as an example data centre switches which require a large number of network and backplane interconnects tightly integrated with the switch logic IC. These interconnects will be on-board and eventually on-package optical modules. Silicon photonics is ideally placed to provide a scalable I/O solution for such applications, as channel data rates move to 50 gigabit and beyond, says Van Campenhout.
But if it is going to take several years to resolve the insertion loss issues for short-reach interconnects, this is a market application that will only start driving significant volumes early in the next decade.
The advent of 400 Gigabit Ethernet and perhaps 800 Gigabit Ethernet after that will be another driver in the coming years.
Other emerging markets include sensors. “Mid infra-red for sensing is a very interesting topic with quite some potential,” says Van Campenhout. “But it is not entirely clear what will be the killer application.”
Sensing is a fragmented application area where many technology solutions exist. “It is too early to figure out what applications an optical sensing device would be competitive against incumbent designs.” But the more integration required, the more competitive silicon photonics will become for such applications, he says.
The Internet of Things will also use sensing but this will be an extremely cost-sensitive market.
“It is not entirely clear if optical technology will be able to meet such cost pressures but if it does, it will drive tremendous volumes and help develop an ecosystem around silicon photonics,” says Van Campenhout.
Further reading:
Imec gears up for the Internet of Things economy, click here
Start-up Sicoya targets chip-to-chip interfaces
“The trend we are seeing is the optics moving very close to the processor,” says Sven Otte, Sicoya’s CEO.
Sicoya was founded last year and raised €3.5 million ($3.9 million) towards the end of 2015. Many of the company’s dozen staff previously worked at the Technical University of Berlin. Sicoya expects to grow the company’s staff to 20 by the year end.
Otte says a general goal shared by silicon photonics developers is to combine the optics with the processor but that the industry is not there yet. “Both are different chip technologies and they are not necessarily compatible,” he says. “Instead we want the ASPIC very close to the processor or even co-packaged in a system-in-package design.”
Vertical-cavity surface-emitting lasers (VCSELs) are used for embedded optics placed alongside chips. VCSELs are inexpensive to make, says Otte, but they need to be packaged with driver chips. A VCSEL also needs to be efficiently coupled to the fibre which also requires separate lenses. ”These are hand-made transceivers with someone using a microscope to assemble,” says Otte. “But this is not scalable if you are talking about hundreds of thousands or millions of parts.”
He cites the huge numbers of Intel processors used in servers. “If you want to put an optical transceiver next to each of those processors, imagine doing that with manual assembly,” says Otte. “It just does not work; not if you want to hit the price points.”
In contrast, using silicon photonics requires two separate chips. The photonics is made using an older CMOS process with 130nm or 90nm feature sizes due to the relatively large dimensions of the optical functions, while a more advanced CMOS process is used to implement the electronics - the control loops, high-speed drivers and the amplifiers - associated with the optical transceiver. If an advanced CMOS process is used to implement both the electronics and optics on the one chip, the photonics dominates the chip area.
“If you use a sophisticated CMOS process then you pay all the money for the electronics but you are really using it for the optics,” says Otte. “This is why recently the two have been split: a sophisticated CMOS process for the electronics and a legacy, older process for the optics.”
Sicoya is adopting a single-chip approach, using a 130nm silicon germanium BiCMOS process technology for the electronics and photonics, due to its tiny silicon photonics modulator. “Really it is an electronics chip with a little bit of optics,” says Otte.
You can’t make a data centre ten times larger, and data centres can’t become ten times more expensive. You need to do something new.
Modulation
The start-up does not use a traditional Mach-Zehnder modulator or the much smaller ring-resonator modulator. The basic concept of the ring resonator is that by varying the refractive index of the ring waveguide, it can build up a large intensity of light, starving light in an adjacent coupled waveguide. This blocking and passing of light is what is needed for modulation.
The size of the ring resonator is a big plus but its operation is highly temperature dependent. “One of its issues is temperature control,” says Otte. “Each degree change impacts the resonant frequency [of the modulator].” Moreover, the smaller the ring-resonator design, the more sensitive it becomes. “You may shrink the device but then you need to add a lot more [controlling] circuitry,” he says.
Stefan Meister, Sicoya’s CTO, explains that there needs to be a diode with a ring resonator to change the refractive index to perform the modulation. The diode must be efficient otherwise, the resonance region is narrow and hence more sensitive to temperature change.
Sicoya has developed its own modulator which it refers to as a node-matched diode modulator. The modulator uses a photonic crystal; a device with a periodic structure which blocks certain frequencies of light. Sicoya’s modulator acts like a Fabry-Perot resonator and uses an inverse spectrum approach. “It has a really efficient diode inside so that the Q factor of the resonator can be really low,” says Meister. “So the issue of temperature is much more relaxed.” The Q factor refers to the narrowness of the resonance region.
Operating based on the inverse spectrum also results in Sicoya’s modulator having a much lower loss, says Meister.
Sicoya is working with the German foundry IHP to develop its technology and claims its modulator has been demonstrated operating at 25 gigabit and at 50 gigabit. But the start-up is not yet ready to detail its ASPIC designs nor when it expects to launch its first product.
5G wireless
However the CEO believes such technology will be needed with the advent of 5G wireless. The 10x increase in broadband bandwidth that the 5G cellular standard promises coupled with the continual growth of mobile subscribers globally will hugely impact data centres.
“You can’t make a data centre ten times larger, and data centres can’t become ten times more expensive, says Otte. “You need to do something new.”
This is where Sicoya believes its ASPICs can play a role.
“You can forward or process ten times the data and you are not paying more for it,” says Otte. “The transceiver chip is not really more expensive than the driver chip.”
ECOC 2015: Reflections
Valery Tolstikhin, head of a design consultancy, Intengent
ECOC was a big show and included a number of satellite events, such as the 6th European Forum on Photonic Integration, the 3rd Optical Interconnect in Data Center Symposium and Market Focus, all of which I attended. So, lots of information to digest.
My focus was mainly on data centre optical interconnects and photonic integration.
Data centre interconnects
What became evident at ECOC is that 50 Gig modulation and the PAM-4 modulation format will be the basis of the next generation (after 100 Gig) data centre interconnect. This is in contrast to the current 100 Gig non-return-to-zero (NRZ) modulation using 25 Gig lanes.
This paves the way towards 200 Gig (4 x PAM-4 lanes at 25 Gig) and 400 Gig (4 x PAM-4 lanes at 50 Gig) as a continuation of quads of 4 x NRZ lanes at 25 Gig, the state-of-the-art data centre interconnect still to take off in terms of practical deployment.
The transition from 100 Gig to 400 Gig seems to be happening much faster than from 40Gig to 100 Gig. And 40 Gig serial finally seems to have gone; who needs 40 Gig when 50 Gig is available?
Another observation is that despite the common agreement that future new deployments should use single-mode fibre rather than multi-mode fibre, given the latter’s severe reach limitation that worsens with modulation speed, the multi-mode fibre camp does not give up easily.
That is because of the tons of multi-mode fibre interconnects already deployed, and the low cost of gallium arsenide 850 nm VCSELs these links use. However, the spectral efficiency of such interconnects is low, resulting in high multi-mode fibre count and the associated cost. This is a strong argument against such fibre.
Now, a short-wave WDM (SWDM) initiative is emerging as a partial solution to this problem, led by Finisar. Both OM3 and OM4 multi-mode fibre can be used, extending link spans to 100m at 25 Gig speeds.
Single mode fibre 4 x 25 Gig QSFP28 pluggables with a reach of up to 2 km, which a year ago were announced with some fanfare, seems to have become more of a commodity.
The SWDM Alliance was announced just before ECOC 2015, with major players like Finisar and Corning on board, suggesting this is a serious effort not to be ignored by the single mode fibre camp.
Lastly, single mode fibre 4 x 25 Gig QSFP28 pluggables with a reach of up to 2 km, which a year ago were announced with some fanfare, seems to have become more of a commodity. Two major varieties – PSM and WDM – are claimed and, probably shipping, by a growing number of vendors.
Since these are pluggables with fixed specs, the only difference from the customer viewpoint is price. That suggests a price war is looming, as happens in all massive markets. Since the current price still are an order of magnitude or more above the target $1/Gig set by Facebook and the like, there is still a long way to go, but the trend is clear.
This reminds me of that I’ve experienced in the PON market: a massive market addressed by a standardised product that can be assembled, at a certain time, using off-the-shelf components. Such a market creates intense competition where low-cost labour eventually wins over technology innovation.
Photonic integration
Two trends regarding photonic integration for telecom and datacom became clear at ECOC 2015.
One positive development is an emerging fabless ecosystem for photonic integrated circuits (PICs), or at least an understanding of a need for such. These activities are driven by silicon photonics which is based on the fabless model since its major idea is to leverage existing silicon manufacturing infrastructure. For example, Luxtera, the most visible silicon component vendor, is a fabless company.
There are also signs of the fabless ecosystem building up in the area of III-V photonics, primarily indium-phosphide based. The European JePPIX programme is one example. Here you see companies providing foundry and design house services emerging, while the programme itself supports access to PIC prototyping through multi-project wafer (MPW) runs for a limited fee. That’s how the ASIC business began 30 to 40 years ago.
A link to OEM customers is still a weak point, but I see this being fixed in the near future. Of course, Intengent, my design house company, does just that: links OEM customers and the foundries for customised photonic chip and PIC development.
As soon as PICs give a system advantage, which Infinera’s chips do, they become a system solution enabler, not merely ordinary components made a different way
The second, less positive development, is that photonic integration continues to struggle to find applications and markets where it will become a winner. Apart from devices like the 100 Gig coherent receiver, where phase control requirements are difficult to meet using discretes, there are few examples where photonic integration provides an edge.
Even a 4 x 25 Gig assembly using discrete components for today’s 100 Gig client side and data centre interconnect has been demonstrated by several vendors. It then becomes a matter of economies of scale and cheap labour, leaving little space for photonic integration to play. This is what happened in the PON market despite photonic integrated products being developed by my previous company, OneChip Photonics.
On a flip side, the example of Infinera shows where the power of photonic integration is: its ability to create more complicated PICs as needed without changing the technology.
One terabit receiver and transmitter chips developed by Infinera are examples of complex photonic circuits, simply undoable by means of an optical sub-assembly. As soon as PICs give a system advantage, which Infinera’s chips do, they become a system solution enabler, not merely ordinary components made a different way.
However, most of the photonic integration players - silicon photonics and indium phosphide alike - still try to do the same as what an optical sub-assembly can do, but more cheaply. This does not seem to be a winning strategy.
And a comment on silicon photonics. At ECOC 2015, I was pleased to see that, finally, there is a consensus that silicon photonics needs to aim at applications with a certain level of complexity if it is to provide any advantage to the customer.
Silicon photonics must look for more complex things, maybe 400 Gig or beyond, but the market is not there yet
For simpler circuits, there is little advantage using photonic integration, least of all silicon photonics-based ones. Where people disagree is what this threshold level of complexity is. Some suggest that 100 Gig optics for data centres is the starting point but I’m unsure. There are discrete optical sub-assemblies already on the market that will become only cheaper and cheaper. Silicon photonics must look for more complex things, maybe 400 Gig or beyond, but the market is not there yet.
One show highlight was the clear roadmap to 400 Gig and beyond, based on a very high modulation speed (50 Gig) and the PAM-4 modulation format, as discussed. These were supported at previous events, but never before have I seen the trend so clearly and universally accepted.
What surprised me, in a positive way, is that people have started to understand that silicon photonics does not automatically solve their problems, just because it has the word silicon in its name. Rather, it creates new challenges, cost efficiency being an important one. The conditions for cost efficient silicon photonics are yet to be found, but it is refreshing that only a few now believe that the silicon photonics can be superior by virtue of just being ‘silicon’.
I wouldn’t highlight one thing that I learned at the show. Basically, ECOC is an excellent opportunity to check on the course of technology development and people’s thoughts about it. And it is often better seen and felt on the exhibition floor than attending the conference’s technical sessions.
For the coming year, I will continue to track data centre interconnect optics, in all its flavours, and photonic integration, especially through a prism of the emerging fabless ecosystem.
Vishnu Shukla, distinguished member technical staff in Verizon’s network planning group.
There were more contributions related to software-defined networking (SDN) and multi-layer transport at ECOC. There were no new technology breakthroughs as much as many incremental evolutions to high-speed optical networking technologies like modulation, digital signal processors and filtering.
I intend to track technologies and test results related to transport layer virtualisation and similar efforts for 400 Gig-and-beyond transport.
Vladimir Kozlov, CEO and founder of LightCounting
I had not attended ECOC since 2000. It is a good event, a scaled down version of OFC but just as productive. What surprised me is how small this industry is even 15 years after the bubble. Everything is bigger in the US, including cars, homes and tradeshows. Looking at our industry on the European scale helps to grasp how small it really is.
What is the next market opportunity for optics? The data centre market is pretty clear now, but what next?
Listening to the plenary talk of Sir David Paine, it struck me how infinite technology is. It is so easy to get overexcited with the possibilities, but very few of the technological advances lead to commercial success.
The market is very selective and it takes a lot of determination to get things done. How do start-ups handle this risk? Do people get delusional with their ideas and impact on the world? I suspect that some degree of delusion is necessary to deal with the risks.
As for issues to track in the coming year, what is the next market opportunity for optics? The data centre market is pretty clear now, but what next?
Silicon photonics: "The excitement has gone"
The opinion of industry analysts regarding silicon photonics is mixed at best. More silicon photonics products are shipping but challenges remain.
Part 1: An analyst perspective
"The excitement has gone,” says Vladimir Kozlov, CEO of LightCounting Market Research. “Now it is the long hard work to deliver products.”
Dale Murray, LightCounting
However, he is less concerned about recent setbacks and slippages for companies such as Intel that are developing silicon photonics products. This is to be expected, he says, as happens with all emerging technologies.
Mark Lutkowitz, principal at consultancy fibeReality, is more circumspect. “As a general rule, the more that reality sets in, the less impressive silicon photonics gets to be,” he says. “The physics is just hard; light is not naturally inclined to work on the silicon the way electronics does.”
LightCounting, which tracks optical component and modules, says silicon photonics product shipments in volume are happening. The market research firm cites Cisco’s CPAK transceivers, and 40 gigabit PSM4 modules shipping in excess of 100,000 units as examples. Six companies now offer 40 gigabit PSM4 products with Luxtera, a silicon photonics player, having a healthy start on the other five.
Indium phosphide and other technologies will not step back and give silicon photonics a free ride
LightCounting also cites Acacia with its silicon photonics-based low-power 100 and 400 gigabit coherent modules. “At OFC, Acacia made a fairly compelling case, but how much of its modules’ optical performance is down to silicon photonics and how much is down to its advanced coherent DSP chip is unclear,” says Dale Murray, principal analyst at LightCounting. Silicon photonics has not shown itself to be the overwhelming solution for metro/ regional and long-haul networks to date but that could change, he says.
Another trend LightCounting notes is how PAM-4 modulation is becoming adopted within standards. PAM-4 modulates two bits of data per symbol and has been adopted for the emerging 400 Gigabit Ethernet standard. Silicon photonics modulators work really well with PAM-4 and getting it into standards benefits the technology, says LightCounting. “All standards were developed around indium phosphide and gallium arsenide technologies until now,” says Kozlov.
You would be hard pressed to find a lot of OEMs or systems integrators that talk about silicon photonics and what impact it is going to have
Silicon photonics has been tainted due to the amount of hype it has received in recent years, says Murray. Especially the claim that optical products made in a CMOS fabrication plant will be significantly cheaper compared to traditional III-V-based optical components.
First, Murray highlights that no CMOS production line can make photonic devices without adaptation. “And how many wafers starts are there for the whole industry? How much does a [CMOS] wafer cost?” he says.
“You would be hard pressed to find a lot of OEMs or systems integrators that talk about silicon photonics and what impact it is going to have,” says Lutkowitz. “To me, that has always said everything.”
Mark Lutkowitz, fibeReality LightCounting highlights heterogeneous integration as one promising avenue for silicon photonics. Heterogeneous integration involves bonding III-V and silicon wafers before processing the two.
This hybrid approach uses the III-V materials for the active components while benefitting from silicon’s larger (300 mm) wafer sizes and advanced manufacturing techniques.
Such an approach avoids the need to attach and align an external discrete laser. “If that can be integrated into a WDM design, then you have got the potential to realise the dream of silicon photonics,” says Murray. “But it’s not quite there yet.”
This poses a real challenge for silicon photonics: it will only achieve low cost if there are sufficient volumes, but without such volumes it will not achieve a cost differential
Murray says over 30 vendors now make modules at 40 gigabit and above: “There are numerous module types and more are being added all the time.” Then there is silicon photonics which has its own product pie split. This poses a real challenge for silicon photonics: it will only achieve low cost if there are sufficient volumes, but without such volumes it will not achieve a cost differential.
“Indium phosphide and other technologies will not step back and give silicon photonics a free ride, and are going to fight it,” says Kozlov. Nor is it just VCSELs that are made in high volumes.
LightCounting expects over 100 million indium phosphide transceivers to ship this year. Many of these transceivers use distributed feedback (DFB) lasers and many are at 10 gigabit and are inexpensive, says Kozlov.
For FTTx and GPON, bi-directional optical subassemblies (BOSAs) now cost $9, he says: “How much lower cost can you get?”
OFC 2015 digest: Part 2
- CFP4- and QSFP28-based 100GBASE-LR4 announced
- First mid-reach optics in the QSFP28
- SFP extended to 28 Gigabit
- 400 Gig precursors using DMT and PAM-4 modulations
- VCSEL roadmap promises higher speeds and greater reach