Infinera’s ICE6 crosses the 100-gigabaud threshold
Coherent discourse 3
- The ICE6 Turbo can send two 800-gigabit wavelengths over network spans of 1,100-1,200km using a 100.4 gigabaud (GBd) symbol rate.
- The enhanced reach can reduce the optical transport equipment needed in a network by 25 to 30 per cent.
Infinera has enhanced the optical performance of its ICE6 coherent engine, increasing by up to 30 per cent the reach of its highest-capacity wavelength transmissions.
The ICE6 Turbo coherent optical engine can send 800-gigabit optical wavelengths over 1,100-1,200km compared to the ICE6’s reach of 700-800km.
ICE6 Turbo uses the same coherent digital signal processor (DSP) and optics as the ICE6 but operates at a higher symbol rate of 100.4GBd.
“This is the first time 800 gigabits can hit long-haul distances,” says Ron Johnson, general manager of Infinera’s optical systems & network solutions group.
Baud rates
Infinera’s ICE6 operates at 84-96GBd to transmit two wavelengths ranging from 200-800 gigabits. This gives a total capacity of 1.6 terabits, able to send 4×400 Gigabit Ethernet (GbE) or 16x100GbE channels, for example.
Infinera’s ICE6’s coherent DSP uses sub-carriers and their number and baud rates are tuned to the higher symbol rate.
The bit rate sent is defined using long-codeword probabilistic constellation shaping (LC-PAS) while Infinera also uses soft-decision FEC gain sharing between the DSP’s two channels.
The ICE6 Turbo adds several more operating modes to the DSP that exploit this higher baud rate, says Rob Shore, senior vice president of marketing at Infinera.
Reach
Infinera says that the ICE6 Turbo can also send two 600-gigabit wavelengths over 4,000km.
“This is almost every network in the world except sub-sea,” says Shore, adding that the enhanced reach will reduce the optical transport equipment needed in a network by 25 to 30 per cent.
“One thousand kilometres sending 2×800 gigabits or 4x400GbE is a powerful thing,” adds Johnson. “We’ll see a lot of traction with the content providers with this.”
Increasing symbol rate
Optical transport system designers continue to push the symbol rate. Acacia, part of Cisco, has announced its next 128GBd coherent engine while Infinera’s ICE6 Turbo now exceeds 100GBd.
Increasing the baud rate boosts the capacity of a single coherent transceiver while lowering the cost and power used to transport data. A higher baud rate can also send the same data further, as with the ICE6 Turbo.
“The original ICE6 device was targeted for 84GBd but it had that much overhead in the design to allow for these higher baud rate modes,” says Johnson. “We strived for 84GBd and technically we can go well beyond 100.4GBd.”
This is common, he adds.
The electronics of the coherent design – the silicon germanium modulator drivers, trans-impedance amplifiers, and analogue-to-digital and digital-to-analogue converters – are designed to perform at a certain level and are typically pushed harder and harder over time.
Baud rate versus parallel-channel designs
Shore believes that the industry is fast approaching the point where upping the symbol rate will no longer make sense. Instead, coherent engines will embrace parallel-channel designs.
Already upping the baud rate no longer improves spectral efficiency. “The industry has lost a vector in which we typically expect improvements generation by generation,” says Shore. “We now only have the vector of lowering cost-per-bit.”
At some point, coherent designs will use multiple DSP cores and wavelengths. What matters will be the capacity of the optical engine rather than the capacity of an individual wavelength, says Shore.
“We have had a lot of discussion about parallelism versus baud rate,” adds Johnson.
Already there is fragmentation with embedded and pluggable coherent optics designs. Embedded designs are optimised for high-performance spectral efficiency while for pluggables cost-per-bit is key.
This highlights that there is more than one optimisation approach, says Johnson: “We have got to develop multiple technologies to hit all those different optimisations.”
Infinera will use 5nm and 3nm CMOS for its future coherent DSPs, optimised for different parts of the network.
Infinera will keep pushing the baud rate but Johnson admits that at some point the cost-per-bit will start to rise.
“At present, it is not clear that doubling the baud rate again is the right answer,” says Johnson. “Maybe it is a combination of a little bit more [symbol rate] and parallelism, or it is moving to 200GBd.”
The key is to explore the options and deliver coherent technology consistently.
“If we put too much risk in one area and drive too hard, it has the potential to push our time-to-market out,” says Johnson.
The ICE6 Turbo will be showcased at the OFC show being held in San Diego in March.
ADVA’s 800-gigabit CoreChannel causes a stir
ADVA’s latest addition to its FSP 3000 TeraFlex platform provides 800-gigabit optical transmission. But the announcement has caused a kerfuffle among its optical transport rivals.
ADVA’s TeraFlex platform supports various coherent optical transport sleds, a sled being a pluggable modular unit that customises a platform’s functionality.
The coherent sleds use Cisco’s (formerly Acacia Communication’s) AC1200 optical engine. Cisco completed the acquisition of Acacia in March.
The AC1200 comprises a 16nm CMOS Pico coherent digital signal processor (DSP) that supports two wavelengths, each up to 600-gigabit, and two photonic integrated circuits (PICs), for a maximum capacity of 1.2 terabits.
The latest sled from ADVA, dubbed CoreChannel, supports an 800-gigabit stream in a single channel.
ADVA states in its press release that the CoreChannel uses “140 gigabaud (GBd) sub-carrier technology” to deliver 800-gigabit over distances exceeding 1,600km.
This, the company says, improves reach by over 50 per cent compared with state-of-the-art 95GBd symbol rate coherent technologies.
It is these claims that have its rivals reacting.
“Despite their claims – they are not using actual digital sub-carriers,” says one executive from a rival optical transport firm, adding that what ADVA is doing is banding two independent 70GBd 400-gigabit wavelengths together and trying to treat that as a single 800-gigabit signal.
“This isn’t necessarily a bad solution for some applications – each network operator can decide that for themselves,” says the executive. However, he stresses that the CoreChannel is not an 800-gigabit single-channel solution and uses 4th generation 16nm CMOS DSP technology rather than the latest 5th generation, 7nm CMOS DSP technology.
A second executive, from another optical transport vendor providing 800-gigabit single-wavelength solutions, adds that ADVA’s claim of 140GBd is too ‘creative’ for a two-lambda solution.
“It’s not a real 800 gigabit. Not that this must be bad, but one should call things as they are,” the spokesperson said. “What matters to the operators is the cost, power consumption, reach and density of a modem; the number of lambdas is more of an internal feature.”
CoreChannel
ADVA confirms it is indeed using Cisco’s Pico coherent DSP to drive two wavelengths, each at 400 gigabits-per-second (Gbps).
“You can say the CoreChannel is a less challenging requirement because we are not driving it [the Pico DSP] to the maximum modulation or constellation complexity,” says Stephan Rettenberger, senior vice president, marketing and investor relations at ADVA. “It is the lower end of what the AC1200 can do.”
Until now the two wavelengths have been combined externally, and have not been integrated from a software or a command-and-control approach.
“The CoreChannel sled is just another addition to the TeraFlex toolbox,” says Rettenberger. “It has one physical line interface that drives an 800Gbps stream using two wavelengths, each one around 70GBd, that are logically and physically combined.”
The resulting two-wavelength 800-gigabit stream sits within a 150GHz channel. However, the channel width can be reduced to 125GHz and even 112.5GHz for greater spectral efficiency.
ADVA says the motivation for the design is the customers’ requirement for lower-cost transport and the ability to easily transport 400 Gigabit Ethernet (GbE) client signals.
“With this 800-gigabit line speed, you can go something like 2,000km, that is 50-100 per cent more than what 95GBd single-wavelengths solutions will do,“ says Rettenberger. “And you can also drive it at 400 gigabits and you can do something like 6,000km.”
The reaches quoted are based on a recent field trial involving ADVA.
ADVA uses a single DSP, similar to the latest 800-gigabit systems from Ciena, Huawei and Infinera. Alongside the DSP are two non-hermetically-sealed PICs whereas the 95GBd indium-phosphide solutions use a single hermetically sealed gold box.
ADVA’s solution also requires two lasers whereas the 800-gigabit single-wavelength solutions use one laser.
“Yes, we have two lasers versus one but that is not killing the cost,” says Rettenberger. “And it is also not killing the power consumption because the PIC is so much more power efficient.”
Rettenberger stresses that ADVA is not saying its offering is necessarily a better solution. “But it is a very interesting way to drive 800 gigabits further than these 95 gigabaud solutions,” says Rettenberger. “It has the same cost, space, power efficiency, just greater reach.”
ADVA also agrees that it is not using electrical sub-carriers such as Infinera uses but it is using optical sub-carrier technology.
These two wavelengths are combined logically and also from a physical port interface point of view to fit within a 150GHz window.
The 95GBd, in contrast, is an interim symbol rate step and the resulting 112.5GHz channel width doesn’t easily fit with legacy 25GHz and 50GHz band increments, says ADVA, while the 150GHz band the CoreChannel sled uses is the same channel width that will be used once single-wavelength 140GBd technology becomes available.
Acacia has also long talked about the merit of doubling the baud rate suggesting Cisco’s successor to the AC1200 will have a 140GBd symbol rate. Such a design is expected in the next year or two.
“We feel this [CoreChannel] implementation is already future-proofed,” says Rettenberger.
ADVA says it undertook this development in collaboration with Acacia.
Acacia announced a dual-wavelength single-channel AC1200 solution in 2019. Then, the company unveiled its AC1200-SC2 that delivers 1.2 terabits over an optical channel.
The SC2 (single chip, single channel) is an upgrade of Acacia’s AC1200 module in that it sends 1.2 terabits using two sub-carriers that fit in a 150GHz-wide channel.
Customer considerations
Choosing an optical solution comes down to five factors, each having its weight depending on the network application, says the first executive.
These are capacity-per-wavelength, cost-per-bit, capacity-per- optical-engine or -module, spectral efficiency and hence capacity-per-fibre, and power-per-bit.
“Each is measured for a given distance/ network application,” says the executive. “And the reason the weight changes for different applications is that the importance of each factor is different at different points in the network. For example, the importance of spectral efficiency changes depending on how expensive it is to light up a link (fibre and line system costs).”
For long-haul and submarine, spectral efficiency is the most important factor, while for metro it is typically cost-per-bit. Meanwhile, for data centre interconnect applications, it’s a mix between cost-per-bit and power-per-bit. Capacity-per-wave and capacity-per-optical-engine are valuable because they can reduce the number of wavelengths and modules that need to be deployed, reducing operating expenses and accelerating service activation.
“The reason that 5th generation [7nm CMOS technology] is superior to fourth generation [16nm] DSP technology is that it provides superior performance in every single one of those key criteria,” says the executive. “This fact minimised any potential benefits that could be achieved by banding together two wavelengths using 4th generation technology when compared to a single wavelength using 5th generation technology.”
“It sounds like others feel we have misled the market; that was not the intent,” says Rettenberger.
ADVA does not make its own coherent DSP so it doesn’t care if the chip is implemented using a 16nm, 7nm or a 5nm CMOS process.
“We are trying to build a good solution for transmitting 400GbE signals and, for us, the Pico chip is a wonderful piece of technology that we have now implemented in four different [sled] variants of TeraFlex.”
