Packaging silicon photonics using passive alignment
- An Israeli start-up is tackling a key packaging challenge for silicon photonics
Teramount has developed a way to simplify the packaging of silicon photonics chips. Instead of using active alignment whereby an external laser is required to carefully align a fibre to the optical die, the Israeli start-up has developed a technology that allows passive alignment.
Hesham Taha“If we want silicon photonics to ramp up to volume, it has to meet CMOS standards both in terms of fabrication and packaging,” says Hesham Taha, Teramount's CEO.
Taha worked at a company developing atomic force microscopy systems before co-founding Teramount. "We got to know of the problem of injecting light into a waveguide and were surprised that the industry was still using active alignment," he says.
This spurred Taha and a colleague to develop optical solutions to match a single-mode fibre core to an optical waveguide, and they founded Teramount in Jerusalem in 2013. "We started real activity at the beginning of 2015 after getting funding," says Taha.
Existing silicon photonics companies either develop their own customised active alignment equipment or outsource the activity to a third party. "If we solve one of the bottlenecks of silicon photonics in terms of packaging, silicon photonics will be more and more adopted," says Taha.
If we want silicon photonics to ramp up to volume, it has to meet CMOS standards both in terms of fabrication and packaging
The design
Teramount's solution includes two elements: a PhotonicsPlug that is flip-chipped onto the silicon photonics die while still part of a wafer, and a 'bump', a design element added on the silicon photonics chip next to the optical waveguide. "Our solution, which we will be selling, is the PhotonicsPlug and we do require them [the designers] to add one element [the bump] to their silicon photonics chip," says Taha.
The main PhotonicsPlug component is a silicon die comprising optics that manipulates the beam using self-aligning optics and focusses it onto the silicon photonics chip via a glass spacer. Teramount’s die also has V-grooves to interface the single-mode ribbon fibre. Teramount says its die is made using an inexpensive mature CMOS process due to the relatively large feature sizes of the optical elements.
The second design element - the bump - is added next to the silicon photonics chip's grating coupler. The grating coupler is one of two techniques used in the industry to interface a fibre to the waveguide, the other being edge coupling.
“We want to place it [the bump] next to the waveguide so that the optics of the PhotonicPlug works in conjunction with it so that it brings the beam to the waveguide with a large tolerance,” says Taha. The bump is accurately placed on the chip using standard lithography techniques.
The resulting tolerance with which the die can be attached to the silicon photonics wafer is up to ± 20 microns in each of the three dimensions such that standard flip-chip machines can attach the PhotonicsPlug to the wafer.
“Flip-chip machines today work with a tolerance of ± 6 microns and can do 1,500 assemblies per hour,” says Taha.
"This is the main philosophy we are bringing here," he says. "Instead of the accurate placement of the fibre next to the grating coupler which requires active alignment, we want to replace that with a cheaper alignment technique that has much better accuracy at the wafer level," says Taha.
Status
Teramount has already shown working devices using the technology. In addition, Teramount is working with several partners and has demonstrated its technology with their silicon photonics chip designs. "With these partners we are doing the integration and qualifying the performance of the device," says Taha. "We will finalise at least two of these partnerships within a few months."
The start-up is also working to enable volume manufacturing by bringing its technology to industrial fabrication plants. This will be completed in the next few months.
Being a small start-up, the company is focussed on developing the grating coupler solution but it has already started work on an edge-coupling technique to a device’s waveguides. Edge coupling is suited to wavelength-division multiplexing (WDM) silicon photonics chips. That is because grating couplers are wavelength-dependent while edge coupling supports a broader range of wavelengths.
Professor Graham Reed: The calm before the storm
Silicon photonics luminaries series
Interview 3: Professor Graham Reed
Despite a half-century track record driving technology, electronics is increasingly calling upon optics for help. “It seems to me that this is a marriage that is really going to define the future,” says Graham Reed, professor of silicon photonics at the University of Southampton’s Optoelectronics Research Centre.
The optics alongside the electronics does not have to be silicon photonics, he says, but silicon as a photonics technology is attractive for several reasons.
“What makes silicon photonics interesting is its promise to enable low-cost manufacturing, an important requirement for emerging consumer applications,” says Reed. And being silicon-based, it is much more compatible than other photonics technologies. “It probably means silicon photonics is going to win out,” he says.
From Surrey to Southampton
Reed has been active in silicon photonics for over 25 years. As an academic at the University of Surrey, his first Ph.D. student was Andrew Rickman, who went on to found Bookham Technology and is now CEO of Rockley Photonics.
Rickman undertook the study of basic optical waveguide structures using silicon. “The first data we got, the waveguide losses were very high, 20 to 30dB per centimetre,” says Reed. “Within a year, we got the losses down to below 1dB per centimetre; that makes it viable.”
The research then broadened to include silicon modulators, a research topic Reed continues to this day.
Everything about silicon photonics is about low cost
The optical modulator is silicon photonics biggest achievement to date, argues Reed. “We were working on modulators in 1991 that worked at 20 megahertz,” he says. “Intel’s Mario Paniccia ribbed me when they got [a modulator] to 1 gigahertz.”
The Surrey group was not focussing on telecom when they started. “I never believed in the early 1990s that these things were going to go as fast as they became,” says Reed. Partly that was because the early work used much larger waveguides and to increase speed, the dimensions need to shrink.
In 2012, Reed and a dozen colleagues moved from the University of Surrey to the University of Southampton. Several factors led to the move. The University of Southampton was interested in the team, given its reputation and the rising importance of silicon photonics, while Reed was keen to make use of the university’s new on-site fabrication plant, which he describes as the best university fab in the UK and probably Europe.
“We were increasing frustrated with the fab facilities around the world,” says Reed. The team used multi-project wafers where companies and institutions have their circuits made on a shared wafer. However, such multi-project wafers have a lower run priority.
“Foundries do a good job but they often take much longer to deliver [the designs] than they aim,” says Reed. Worst case, it can take over three years to receive the chip design back. Given a project cycle typically lasts three years, this is a non-starter, he says: “Having a fab that you have a lot of control over is a big attraction”.
Research focus
Reed’s group is regularly approached by companies from all over the world. But it wasn't always like that. In the 1990s, getting funding to research silicon photonics was a challenge, he says.
The companies now contacting Reed’s group are either in the field and have a difficulty, or they want to enter the marketplace. “They want particular work done or a particular device worked upon,” he says.
Intel is one company that worked with Reed when they started their silicon photonics programme some dozen years ago.
Reed’s group’s research covers the development of individual optical components as well as systems. Much of the work is focussed on telecom and datacom, given that is where silicon photonics is most established, but the group is also conducting work using silicon photonics for longer wavelengths - 2 to 18 microns - known as the mid infra-red region.
Mid infra-red is an emerging field, says Reed: “People have seen the success of existing silicon photonics and are applying it to longer wavelengths.”
Such wavelengths are suited for sensing applications. “A lot of nasties - chemicals you’d want to sense - have characteristic absorption lines in this longer wavelength range,” he says.
Things also become easier at the longer wavelengths because the dimensions of the silicon features are more relaxed. However, additional materials are required that are transparent at these longer wavelengths, and these platforms all need developing. “Longer wavelengths equate to bigger waveguides; what gets more difficult are the sources and the detectors,” says Reed.
A third research activity his group is tackling is ongoing silicon photonics challenges such as wafer-scale testing, passive alignment, lowering power consumption and thermal stability issues.
Optical device work
Reed cites a low-channel-count multiplexer as an example of its research work on basic optical devices with the goal of helping commercialise silicon photonics.
“One of the issues in silicon photonics is to make things reliable and high yield,” says Reed. “One way to look at that is you need simplicity.”
The group has developed an angled multi-mode interference (MMI) multiplexer suited for 4 or 8 channel designs.
“It is so simple,” says Reed. The multiplexer is made in a single etch step and is based on large multi-mode waveguides that are more resilient to fabrication errors and layer thickness variations. The design is also more thermally stable than single-mode waveguides.
Another area is ring resonators - useful devices that can be used for a variety of tasks including modulation but which are sensitive to layer thickness variations as well as thermal stability issues. “If anyone is going to adopt ring resonators they need to find a way to make them athermal,” says Reed. “And they need a way to tune or trim to operate them to the resonance they need.”
Systems work
The group’s systems work addresses some of the same issues as the large systems vendors. However, the group is careful in the topics it chooses given their more modest university resources. “We are looking at more complex modulation systems but probably not for long haul communications,” says Reed.
Another research activity is looking at alternative ways to combine components. Using silicon photonics for integration in the mid infra-red range may give a new lease of life to the lab-on-a-chip concept. “People have talked about it for a long while but it hasn't really happened,” says Reed. “If you can do these things in a reliable and low-cost manner, maybe disposable chips are viable again.”
Silicon photonics challenges
Two current manufacturing challenges Reed highlights are the issues of passive alignment and wafer-scale testing.
Coupling the laser to a fibre or the silicon chip’s waveguide using passive alignment remains an ongoing challenge. “Everything about silicon photonics is about low cost,” says Reed. At present to attach a laser, it is typically turned on and aligned to the chip’s waveguide. This requires manual intervention and is time-consuming.
“The ideal scenario is to put a fibre down and it couples to the waveguide or laser and somehow you have aligned it,” he says. The challenge is the discrepancy in dimensions between the 10-micron fibre core and the waveguide, which is typically between 0.35- and 0.5-microns wide. Work is on-going to use mode converters or grating couplers such that the resulting optical loss is low enough to make passive alignment viable.
All these events are consistent with this field of technology pointing to mass markets
Wafer-scale testing remains another challenge. Grating couplers are one way designs can be tested while still on the silicon wafer. But these typically only allow the whole circuit to be tested - either it works or not - but you can’t test individual components. “If you are going to mimic the successes of electronics, you need to test more comprehensibly than that,” says Reed.
His group has developed an erasable grating that can be placed either side of a critical component to test it. These gratings can then be removed from the final circuit by using local laser annealing.
Reed expects the industry to overcome all these manufacturing challenges: “But it still means somebody has to have the brilliant idea”.
He is also somewhat surprised that there are not more silicon photonics products on the market, especially considering the huge investment in the technology made by some of the larger companies over the last decade.
He describes what is happening now as silicon photonics’ quiet period. Partly it is due to the vendors working to commercialise their technologies, partly it is the systems vendors that are developing next-generation products are evaluating the various technologies. “Until somebody jumps and that market takes off - and somebody will jump,” he says. “Then there will be ferocious activity.”
Opportunities
Reed is measured when assessing the future opportunities for the technology.
“It is not something that we strategise about - it is not what we do - but we get insights from time to time because of the people we work with and what they want,” he says. “The crucial thing is what facilitates the mass market because silicon photonics is really trying to bring photonics to the mass market.”
Reed does believe silicon photonics is disruptive: “If you look at the origins of what a disruptive technology is, it is a technology that works in one field but then it performs so well, it crosses the boundary into other areas”.
Silicon photonics was initially regarded as a short-reach technology but once the performance of its modulators started to drastically increase, the technology crossed the boundary into long-haul research, he notes. “That is the definition of a disruptive technology,” he says.
He also believes the technology has passed its tipping point. As evidence, he points to the investment made by the large companies and says it is inevitable that they will launch products: “So in that sense, the tipping point has already been and gone”.
In addition, he highlights the American Institute for Manufacturing Integrated Photonics (AIM Photonics) venture, the $610 million public and private funded initiative set up in 2015 to advance silicon photonics-based manufacturing.
“All these events are consistent with this field of technology pointing to mass markets,” says Reed. “If this was going to be indium phosphide that did that, why did not all that activity happen years ago?”