OFC announcements and market trends
More compact transceiver designs at 10, 40 and 100 Gigabit, advancements in reconfigurable optical add-drop multiplexer (ROADM) technology and parallel optical engine developments were all in evidence at this year’s OFC/NFOEC show held in Los Angeles in March.
“MSAs are designed by committee, and when you have a committee you throw away innovation and you throw away time-to-market”
Victor Krutul, Avago Technologies
Finisar said that the show was one of the busiest in recent years. “There was an increasing system-vendor presence at OFC, and there was a lot more interest from investor analysts,” says Rafik Ward, vice president of marketing at Finisar.
Ethernet interfaces
Opnext demonstrated an IEEE 100GBASE-ER4 module design at the show, the 100 Gigabit Ethernet (GbE) standard with a 40km reach. Based on the company’s CFP-based 100GBASE-LR4 10km module, the design uses a semiconductor optical amplifier (SOA) on the receive path to achieve the extended reach. The IEEE standard calls for an SOA in front of the photo-detectors for the 100GBASE-ER4 interface.
“We don’t have that [SOA] integrated yet, we are just showing the [design] feasibility,” says Jon Anderson, director of technology programme at Opnext. The extended reach interface will be used to connect IP core routers to transport system when the two platforms reside in separate facilities. Such a 40km requirement for a 100GbE interface is not common but is an important one to meet, says Anderson.
Opnext’s first-generation LR4, currently shipping, is a discrete design comprising four discrete transmitter optical sub-assemblies (TOSAs) and four receiver optical sub-assemblies (ROSAs) and an optical multiplexer and demultiplexer. The company’s next-generation design will integrate the four lasers and the optical multiplexer into a package and will be used in future more compact CFP2 and CFP4 modules.
The CFP2 module is half the size of the CFP module and the CFP4 is a quarter. In terms of maximum power, the CFP module is rated at 32W, the CFP2 12W and the CFP4 5W. “The CFP4 is a little bit wider and longer than the QSFP,” says Anderson. The first CFP2 modules are expected to become available in 2012 and the CFP4 in 2013.
System vendors are interested in the CFP4 as they want to support over one terabit of capacity on a 15-inch faceplate. Up to 16 ports can be supported –1.6Tbps – on a faceplate using the CFP4, and using a “belly-to-belly” configuration two rows of 16 ports will be possible, says Anderson.
Finisar demonstrated a distributed feedback laser (DFB) laser-based CFP module at OFC that implements the 10km 100GBASE-LR4 standard. The adoption of DFB lasers promises significant advantages compared to existing first-generation -LR4 modules that use electro-absorption modulated lasers (EMLs). “If you look at current designs, ours included, not only do they use EMLs which are significantly more expensive, but each is in its own package and has its own thermo-electric cooler,” says Ward.
Finisar’s use of DFBs means an integrated array of the lasers can be packaged and cooled using a single thermo-electric cooler, significantly reducing cost and nearly halving the power to 12W. “Now that the power [of the DFB-based] LR4 is 12W, we can place it within a CFP2 with its 25-28 Gigabit-per-second (Gbps) electrical I/O,” says Ward.
Moving to the faster input/output (I/O) compared to the CFP’s 10Gbps I/O means that that serialiser/ deserialiser (serdes) chipset can be replaced with simpler clock data recovery (CDR) circuitry. “By the time we move to the CFP4, we remove the CDRs completely,” says Ward. “It’s an un-retimed interface.” Finisar’s existing -LR4 design already uses an integrated four-photodetector array.
An early application of the 100GbE -LR4, as with the -ER4, is linking core routers with optical transport systems in operators’ central offices. Many Ethernet switch vendors have chosen to focus their early high-data efforts at 40GbE but Finisar says the move to 100GbE has started.
Finisar argues that the adoption of DFBs will ultimately prove the cost-benefits of a 4-channel 100GbE design which faces competition from the emerging 10x10 multi-source agreement (MSA). “Everything we have heard about the 10x10 [MSA] has been around cost,” says Ward. “The simple view inside Finisar is that by the time the Gen2 100GbE module that we showed at OFC gets to market, this argument [4x25Gig vs. 10x10Gig] will be a moot point.”
“40Gig is definitely still strong and healthy”
Jon Anderson, Opnext
By then the second-generation -LR4 module design will be cost competitive if not even lower cost than the 10x10 MSA. “If you look at optoelectronic components, at the end of the day what really drives cost is yield,” says Ward. “If we can get our yields of 25Gig DFBs down to a level that is similar to 10Gig DFB yields- it doesn’t have to match, just in the ballpark - then we have a solution where the 4x25Gig looks like a 4x10Gig solution and then I believe everyone will agree that 4x25Gig is a less expensive architecture.” Finisar expects the Gen2 CFP -LR4 in production by the first half of 2012.
Opnext demonstrated a 40GBASE- LR4 (40Gbps, up to 10km) standard in a QSFP+ module at OFC. Anderson says it is seeing demand for such a design from data centre operators and from switch and transport vendors.
Avago Technologies announced a 40Gbps QSFP+ module at OFC that implements the 100m IEEE 40GBASE-SR4. “It will interoperate with Avago’s SFP+ modules,” says Victor Krutul, director of marketing for the fibre optics division at Avago Technologies. The QSFP+ can interface to another QSFP+ module or to four 10Gbps SFP+ modules.
Avago also announced a proprietary mini-SFP+ design, 30% smaller than the standard SFP+ but which is electrically compatible. According to Krutul, the design came about following a request from one of its customers: “What it allows is the ability to have 64 ports on the front [panel] rather than 48.”
Did Avago consider making the mini-SFP+ design an MSA? “What we found with MSAs is that they are designed by committee, and when you have a committee you throw away innovation and you throw away time-to-market,” says Krutul.
Krutul was previously a marketing manager for Intel’s LightPeak before joining Avago over half a year ago.
“There was an increasing system-vendor presence at OFC, and there was a lot more interest from investor analysts”
Rafik Ward, Finisar.
Line-side interfaces
Opnext will be providing select customers with its 100Gbps DP-QPSK coherent module for trialling this quarter. The module has a 5-inch by 7-inch footprint and uses a 168-pin connector. “We are working to try and meet the OIF spec [with regard power consumption] which is 80W.” says Anderson. “It is challenging and it may not be met in the first generation [design].”
The company is also moving its 40Gbps 2km very short reach (VSR) transponder to support the IEEE 40GBASE-FR standard within a CFP module, dubbed the “tri-rate” design. “The 40BASE-FR has been approved, with the specification building on the ITU’s 40Gig VSR,” says Anderson. “It continues to support the [OC-768] SONET/SDH rate, it will support the new OTN ODU3 40Gbps and the intermediate 40 Gigabit Ethernet.”
Opnext and Finisar are both watching with interest the emerging 100Gbps direct detection market, an alternative to 100 Gigabit coherent aimed shorter reach metro applications.
“We certainly are watching this segment and do have an interest, but we don’t have any product plans to share at this point,” says Anderson.
“The [100Gbps] direct-detection market is very interesting,” says Ward. Coherent is not going to be the only way people will deploy 100Gbps light paths. “There will be a market for shorter reach, lower performance 100 Gigabit DWDM that will be used primarily in datacentre-to-datacentre,” he says. Tier 2 and tier 3 carriers will also be interested in the technology for use in shorter metro reaches. “There is definitely a market for that,” says Ward.
Opnext also announced its small form-factor – 3.5-inch by 4.5-inch - 40Gbps DPSK module. “With a smaller form factor, the next generation could move to a CFP type pluggable,” says Anderson. “But that is if our customers are interested in migrating to a pluggable design for DPSK and DQPSK.”
Are there signs that the advent of 100 Gigabit is affecting 40Gbps uptake? “We definitely not seeing that,” says Anderson. “We are continuing to see good solid demand for both 40G line side – DPSK and DQPSK – and a lot of pull to being this tri-rate VSR.”
Such demand is not just from China but also North Ametican carriers. “40 Gig is definitely still strong and healthy,” says Anderson “But there are some operators that are waiting to see how 100G does and approved in for major build-outs.”
At 10Gbps, Opnext also had on show a tunable TOSA for use in an XFP module, while Finisar announced an 80km, 10Gbps SFP+ module. “SFP+ has become a very successful form factor at 10Gbps,” says Ward. “All the market data I see show SFP+ leads in overall volumes deployed by a significant margin.” Its success has been achieved despite being a form factor was not designed to achieve all the 10Gbps reaches required initially. This is some achievement, says Ward, since the XFP+ form factor used for 80km has a power rating of 3.5W while the 80km SFP+ has to work within a less than 2W upper limit.
Parallel Optics
Avago detailed its main parallel optic designs: the CXP module and its two optical engine designs.
The company claims it seeing much interested from high-performance computing vendors such as IBM and Fujitsu for its CXP 120 Gigabit (12x10Gbps) parallel transceiver module. Avago is sampling the module and it will start shipping in the summer.
The company also announced the status of its embedded parallel optics devices (PODs). Such parallel optic designs offer several advantages, says Krutul. Embedding the optics on the motherboard offers greater flexibility in cooling since the traditional optics is normally at the edge of the card, furthest away from the fans. Such optics also simplify high-speed signal routing on the printed circuit board since fibre is used.
Avago offers two designs – the 8x8mm MicroPod and the 22x18mm MiniPod. The 12x10Gbps MicroPods are being used in IBM’s Blue Gene computer and Avago says it is already shipping tens of thousands of the devices a month. “The [MicroPod’s] signal pins have a very tight pitch and some of our customers find that difficult to do,” says Krutul. The MiniPod design tackles this by using the MicroPod optical engine but a more relaxed pitch. At OFC, Avago said that the MiniPod is now sampling.
Gridless ROADMs
Finisar demonstrated what it claims is the first gridless wavelength-selective switch (WSS) module at the show. A gridless ROADM supports variable channel widths beyond the fixed International Telecommunication Union's (ITU) defined spacings. Such a capability enables ROADMs to support variable channel spacings that may be required for transmission rates beyond 100Gbps: 400Gbps, 1Tbps and beyond.
“We have an increasing amount of customer interest in this [FlexGrid], and from what we can tell, there is also an increasing amount of carrier interest as well,” says Ward, adding that the company is already shipping FlexGrid WSSs to customers.
Finisar is a contributing to the ongoing ITU work to define what the grid spacings and the central channels should be for future ROADM deployments. Finisar demonstrated its FlexGrid design implementing integer increments of 12.5GHz spacing. “We could probably go down to 1GHz or even lower than that,” says Ward. “But the network management system required to manage such [fine] granularity would become incredibly complicated.” What is required for gridless is a balance between making good use of the fibre’s spectrum while ensuring the system in manageable, says Ward.
Infinera details Terabit PICs, 5x100G devices set for 2012
Infinera has given first detail of its terabit coherent detection photonic integrated circuits (PICs). The pair - a transmitter and a receiver PIC – implement a ten-channel 100 Gigabit-per-second (Gbps) link using polarisation multiplexing quadrature phase-shift keying (PM-QPSK). The Infinera development work was detailed at OFC/NFOEC held in Los Angeles between March 6-10.
Infinera has recently demonstrated its 5x100Gbps PIC carrying traffic between Amsterdam and London within Interoute Communications’ pan-European network. The 5x100Gbps PIC-based system will be available commercially in 2012.
“We think we can drive the system from where it is today – 8 Terabits-per-fibre - to around 25 Terabits-per-fibre”
Dave Welch, Infinera
Why is this significant?
The widespread adoption of 100Gbps optical transport technology will be driven by how quickly its cost can be reduced to compete with existing 40Gbps and 10Gbps technologies.
Whereas the industry is developing 100Gbps line cards and optical modules, Infinera has demonstrated a 5x100Gbps coherent PIC based on 50GHz channel spacing while its terabit PICs are in the lab.
If Infinera meets its manufacturing plans, it will have a compelling 100Gbps offering as it takes on established 100Gbps players such as Ciena. Infinera has been late in the 40Gbps market, competing with its 10x10Gbps PIC technology instead.
40 and 100 Gigabit
Infinera views 40Gbps and 100Gbps optical transport in terms of the dynamics of the high-capacity fibre market. In particular what is the right technology to get most capacity out of a fibre and what is the best dollar-per-Gigabit technology at a given moment.
For the long-haul market, Dave Welch, chief strategy officer at Infinera, says 100Gbps provides 8 Terabits (Tb) of capacity using 80 channels versus 3.2Tb using 40Gbps (80x40Gbps). The 40Gbps total capacity can be doubled to 6.4Tb (160x40Gbps) if 25GHz-spaced channels are used, which is Infinera’s approach.
“The economics of 100 Gigabit appear to be able to drive the dollar-per-gigabit down faster than 40 Gigabit technology,” says Welch. If operators need additional capacity now, they will adopt 40Gbps, he says, but if they have spare capacity and can wait till 2012 they can use 100Gbps. “The belief is that they [operators] will get more capacity out of their fibre and at least the same if not better economics per gigabit [using 100Gbps],” says Welch. Indeed Welch argues that by 2012, 100Gbps economics will be superior to 40Gbps coherent leading to its “rapid adoption”.
For metro applications, achieving terabits of capacity in fibre is less of a concern. What matters is matching speeds with services while achieving the lowest dollar-per-gigabit. And it is here – for sub-1000km networks – where 40Gbps technology is being mostly deployed. “Not for the benefit of maximum fibre capacity but to protect against service interfaces,” says Welch, who adds that 40 Gigabit Ethernet (GbE) rather than 100GbE is the preferred interface within data centres.
Shorter-reach 100Gbps
Companies such as ADVA Optical Networking and chip company MultiPhy highlight the merits of an additional 100Gbps technology to coherent based on direct detection modulation for metro applications (for a MultiPhy webinar on 100Gbps direct detection, click here). Direct detection is suited to distances from 80km up to 1000km, to connect data centres for example.
Is this market of interest to Infinera? “This is a great opportunity for us,” says Welch.
The company’s existing 10x10Gbps PIC can address this segment in that it is least 4x cheaper than emerging 100Gbps coherent solutions over the next 18 months, says Welch, who claims that the company’s 10x10Gbps PIC is making ‘great headway’ in the metro.
“If the market is not trying to get the maximum capacity but best dollar-per-gigabit, it is not clear that full coherent, at least in discrete form, is the right answer,” says Welch. But the cost reduction delivered by coherent PIC technology does makes it more competitive for cost-sensitive markets like metro.
A 100Gbps coherent discrete design is relatively costly since it requires two lasers (one as a local oscillator (LO - see fig 1 - at the receiver), sophisticated optics and a high power-consuming digital signal processor (DSP). “Once you go to photonic integration the extra lasers and extra optics, while a significant engineering task, are not inhibitors in terms of the optics’ cost.”
Coherent PICs can be used ‘deeper in the network’ (closer to the edge) while shifting the trade-offs between coherent and on-off keying. However even if the advent of a PIC makes coherent more economical, the DSP’s power dissipation remains a factor regarding the tradeoff at 100Gbps line rates between on-off keying and coherent.
Welch does not dismiss the idea of Infinera developing a metro-centric PIC to reduce costs further. He points out that while such a solution may be of particular interest to internet content companies, their networks are relatively simple point-to-point ones. As such their needs differ greatly from cable operators and telcos, in terms of the services carried and traffic routing.
PIC challenges
Figure 1: Infinera's terabit PM-QPSK coherent receiver PIC architecture
There are several challenges when developing multi-channel 100Gbps PICs. “The most difficult thing going to a coherent technology is you are now dealing with optical phase,” says Welch. This requires highly accurate control of the PIC’s optical path lengths.
The laser wavelength is 1.5 micron and with the PIC's indium phosphide waveguides this is reduced by a third to 0.5 micron. Fine control of the optical path lengths is thus required to tenths of a wavelength or tens of nanometers (nm).
Achieving a high manufacturing yield of such complex PICs is another challenge. The terabit receiver PIC detailed in the OFC paper integrates 150 optical components, while the 5x100Gbps transmit and receive PIC pair integrate the equivalent of 600 optical components.
Moving from a five-channel (500Gbps) to a ten-channel (terabit) PIC is also a challenge. There are unwanted interactions in terms of the optics and the electronics. “If I turn one laser on adjacent to another laser it has a distortion, while the light going through the waveguides has potential for polarisation scattering,” says Welch. “It is very hard.”
But what the PICs shows, he says, is that Infinera’s manufacturing process is like a silicon fab’s. “We know what is predictable and the [engineering] guys can design to that,” says Welch. “Once you have got that design capability, you can envision we are going to do 500Gbps, a terabit, two terabits, four terabits – you can keep on marching as far as the gigabits-per-unit [device] can be accomplished by this technology.”
The OFC post-deadline paper details Infinera's 10-channel transmitter PIC which operates at 10x112Gbps or 1.12Tbps.
Power dissipation
The optical PIC is not what dictates overall bandwidth achievable but rather the total power dissipation of the DSPs on a line card. This is determined by the CMOS process used to make the DSP ASICs, whether 65nm, 40nm or potentially 28nm.
Infinera has not said what CMOS process it is using. What Infinera has chosen is a compromise between “being aggressive in the industry and what is achievable”, says Welch. Yet Infinera also claims that its coherent solution consumes less power than existing 100Gbps coherent designs, partly because the company has implemented the DSP in a more advanced CMOS node than what is currently being deployed. This suggests that Infinera is using a 40nm process for its coherent receiver ASICs. And power consumption is a key reason why Infinera is entering the market with a 5x100Gbps PIC line card. For the terabit PIC, Infinera will need to move its ASICs to the next-generation process node, he says.
Having an integrated design saves power in terms of the speeds that Infinera runs its serdes (serialiser/ deserialiser) circuitry and the interfaces between blocks. “For someone else to accumulate 500Gbps of bandwdith and get it to a switch, this needs to go over feet of copper cable, and over a backplane when one 100Gbps line card talks to a second one,” says Welch. “That takes power - we don’t; it is all right there within inches of each other.”
Infinera can also trade analogue-to-digital (A/D) sampling speed of its ASIC with wavelength count depending on the capacity required. “Now you have a PIC with a bank of lasers, and FlexCoherent allows me to turn a knob in software so I can go up in spectral efficiency,” he says, trading optical reach with capacity. FlexCoherent is Infinera’s technology that will allow operators to choose what coherent optical modulation format to use on particular routes. The modulation formats supported are polarisation multiplexed binary phase-shift keying (PM-BPSK) and PM-QPSK.
Dual polarisation 25Gbaud constellation diagrams
What next?
Infinera says it is an adherent of higher quadrature amplitude modulation (QAM) rates to increase the data rate per channel beyond 100Gbps. As a result FlexCoherent in future will enable the selection of higher-speed modulation schemes such as 8-QAM and 16-QAM. “We think we can drive the system from where it is today –8 Terabits-per-fibre - to around 25 Terabits-per-fiber.”
But Welch stresses that at 16-QAM and even higher level speeds must be traded with optical reach. Fibre is different to radio, he says. Whereas radio uses higher QAM rates, it compensates by increasing the launch power. In contrast there is a limit with fibre. “The nonlinearity of the fibre inhibits higher and higher optical power,” says Welch. “The network will have to figure out how to accommodate that, although there is still significant value in getting to that [25Tbps per fibre]” he says.
The company has said that its 500 Gigabit PIC will move to volume manufacturing in 2012. Infinera is also validating the system platform that will use the PIC and has said that it has a five terabit switching capacity.
Infinera is also offering a 40Gbps coherent (non-PIC-based) design this year. “We are working with third-party support to make a module that will have unique performance for Infinera,” says Welch.
The next challenge is getting the terabit PIC onto the line card. Based on the gap between previous OFC papers to volume manufacturing, the 10x100Gbps PIC can be expected in volume by 2014 if all goes to plan.