Imec eyes silicon photonics to solve chip I/O bottleneck
In the second and final article, the issue of adding optical input-output (I/O) to ICs is discussed with a focus on the work of the Imec nanoelectronics R&D centre that is using silicon photonics for optical I/O.
Part 2: Optical I/O
Imec has demonstrated a compact low-power silicon-photonics transceiver operating at 40 gigabits per second (Gbps). The silicon photonics transceiver design also uses 14nm FinFET CMOS technology to implement the accompanying driver and receiver electronics.
Joris Van Campenhout“We wanted to develop an optical I/O technology that can interface to advanced CMOS technology,” says Joris Van Campenhout, director of the optical I/O R&D programme at Imec. “We want to directly stick our photonics device to that mainstream CMOS technology being used for advanced computing applications.”
Traditionally, the Belgium nanoelectronics R&D centre has focussed on scaling logic and memory but in 2010 it started an optical I/O research programme. “It was driven by the fact that we saw that electrical I/O doesn’t scale that well,” says Van Campenhout. Electrical interfaces have power, space and reach issues that get worse with each hike in transmission speed.
Imec is working with partner companies to research optical I/O. The players are not named but include semiconductor foundries, tool vendors, fabless chip companies and electronic design automation tools firms. The aim is to increase link capacity, bandwidth density - a measure of the link capacity that can be crammed in a given space - and reach using optical I/O. The research’s target is to achieve between a 10x to 100x in scaling.
The number of silicon photonics optical I/O circuits manufactured each year remains small, says Imec, several thousand to ten thousand semiconductor wafers at most. But Imec expects volumes to grow dramatically over the next five years as optical interconnects are used for ever shorter reaches, a few meters and eventually below one meter.
“That is why we are participating in this research, to put together building blocks to help in the technology pathfinding,” says Van Campenhout.
We wanted to develop an optical I/O technology that can interface to advanced CMOS technology
Silicon photonics transceiver
Imec has demonstrated a 1330nm optical transceiver operating at 40Gbps using non-return-to-zero signalling. The design uses hybrid integration to combine silicon photonics with 14nm FinFET CMOS electronics. The resulting transceiver occupies 0.025 mm2, the area across the combined silicon photonics and CMOS stack for a single transceiver channel. This equates to a bandwidth density of 1.6 terabit-per-second/mm2.
The silicon photonics and FinFET test chips each contain circuitry for eight transmit and eight receive channels. Combined, the transmitter path comprises a silicon photonics ring modulator and a FinFET differential driver while the receiver uses a germanium-based photo-detector and a first-stage FinFET trans-impedance amplifier (TIA).
The transceiver has an on-chip power consumption of 230 femtojoules-per-bit, although Van Campenhout stresses that this is a subset of the functionality needed for the complete link. “This number doesn’t include the off-chip laser power,” he says. “We still need to couple 13dBm - 20mW - of optical power in the silicon photonics chip to close the link budget.” Given the laser has an efficiency of 10 to 20 percent, that means another 100mW to 200mW of power.
That said, an equivalent speed electrical interface has an on-chip power consumption of some 2 picojoules-per-bit so the optical interface still has some margin to better the power efficiency of the equivalent electrical I/O. In turn, the optical I/O’s reach using single-mode fibre is several hundred meters, far greater than any electrical interface.
Imec is confident it can increase the optical interface’s speed to 56Gbps. The layout of the CMOS circuits can be improved to reduce internal parasitic capacitances while Imec has already improved the ring modulator design compared to the one used for the demonstrator.
“We believe that with a few design tweaks we can get to 56Gbps comfortably,” says Van Campenhout. “After that, to go faster will require new technology like PAM-4 rather than non-return-to-zero signalling.”
Imec has also tested four transmit channels using cascaded ring modulators on a common waveguide as part of work to add a wavelength-division multiplexing capability.
Transceiver packaging
The two devices - the silicon photonics die and the associated electronics - are combined using chip-stacking technology.
Both devices use micro-bumps with a 50-micron pitch with the FinFET die flip-chipped onto the silicon photonics die. The combined CMOS and silicon photonics assembly is glued on a test board and wire-bonded, while the v-groove fibre arrays are attached using active alignment. The fibre-to-chip coupling loss, at 4.5dB in the demonstration, remains high but the researchers say this can be reduced, having achieved 2dB coupling losses in separate test chips.
Source: Imec.
Imec is also investigating using through-silicon vias (TSV) technology and a silicon photonics interposer in order to replace the wire-bonding. TSVs deliver better power and ground signals to the two dies and enable high-speed electrical I/O between the transceiver and the ASIC such as a switch chip. The optics and ASIC could be co-packaged or the transceiver used in an on-board optics design next to the chip.
“We have already shown the co-integration of TSVs with our own silicon photonics platform but we are not yet showing the integration with the CMOS die,” says Van Campenhout. “Something we are working on.”
Co-packaging the optics with silicon will come at a premium cost
Applications
The first ICs to adopt optical I/O will be used in the data centre and for high-performance computing. The latest data centre switch ICs, with a capacity of 12.8 terabits, are implemented using 16nm CMOS. Moving to a 7nm CMOS process node will enable capacities of 51.2 terabits. “These are the systems where the bandwidth density challenge is the largest,” says Van Campenhout.
But significant challenges must be overcome before this happens, he says: “I think we all agree that bringing optics deeply integrated into such a product is not a trivial thing.”
Co-packaging the optics with silicon will come at a premium cost. There are also reliability issues to be resolved and greater standardisation across the industry will be needed as to how the packaging should be done.
Van Campenhout expects this will only happen in the next four to five years, once the traffic-handling capacity of switch chips doubles and doubles again.
Imec has seen growing industry interest in optical I/O in the last two years. “We have a lot of active interactions so interest is accelerating now,” says Van Campenhout.
The ecosystem for silicon photonics starts to take shape
Silicon photonics luminaries series
Interview 6: imec - Philippe Absil and Joris Van Campenhout
Imec has a unique vantage point when it comes to the status and direction of silicon photonics.
The Belgium nano-electronics research centre gets to see prototype designs nearing commercialisation due to its silicon photonics integration platform and foundry service. “We allow companies to build prototypes using a robust silicon photonics technology,” says Philippe Absil, department director for 3D and optical technologies at imec.
Philippe Absil
Imec also works intimately with several partners on longer-term research, one being Huawei. This optical I/O R&D activity is part of imec’s CORE CMOS scaling R&D programme which as well as Huawei includes GlobalFoundries, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony and TSMC. The research is sufficiently far ahead to be deemed pre-competitive such that all the firms collaborate.
For silicon photonics, the optical I/O research includes optical integration schemes, new device concepts and new materials. “The aim is to bring silicon photonics technology to the next level in order to resolve today’s challenges,” says Absil.
Assured future
Imec is confident about silicon photonics’ future but stresses an ecosystem for the technology needs to be in place first. This means having more than one foundry, suitable equipment to reduce the cost of testing silicon photonics circuits, and developing packaging solutions.
“These elements are being developed and the ecosystem is coming together nicely,” says Joris Van Campenhout, programme director for optical I/O at imec.
Another encouraging sign is the strong industry interest in the technology in the last two years. It was mainly academics that were interested in imec's multi-wafer project service but now there is strong demand from companies as well; companies bringing products to market.
Silicon photonics is not a one-off technology; it has value for several generations
Systems scaling is what gives imec confidence that silicon photonics will not end up a niche technology. “Look at the cloud economy and cloud data centres, these systems need to scale continually,” says Van Campenhout. “A lot of effort is being put into scaling, and interconnect is an essential part of such systems.”
Moreover, there are few technologies to deliver such scalability, which is why many of the bigger systems companies are investing in silicon photonics. “Silicon photonics is not a one-off technology; it has value for several generations," says Van Campenhout. “That is really the potential of silicon photonics and that is where the disruption lies.”
Challenges
One focus for imec and its partners is to reduce the overall insertion loss of silicon photonics circuits for short-reach interconnect applications. Such short-reach links span distances of up to a few meters, a market segment currently addressed using advanced copper cabling or VCSEL-based optical interconnects.
Joris Van Campenhout
Because of the relatively high insertion loss of silicon photonics designs, it is not possible to achieve a sufficiently low-power consumption for such links. “That is a show-stopper because it prevents us closing link budgets,” says Van Campenhout. A link budget refers to the gain and losses across the elements making up the optical link such as the laser, modulator, optical fibre and receiver circuitry.
In order to drive up volumes, silicon photonics needs to become more competitive at shorter reaches where VCSELs are still the mainstream optical technology
The team is tackling the loss issue on two fronts: reducing the insertion loss between the fibre and the waveguide, and reducing the modulator's insertion loss which still exceeds that of other optical technologies.
“For these two parts of the technology, further improvements are required to reduce the overall losses,” says Van Campenhout. “That will enable us to be competitive at shorter distances.” These are engineering challenges, he stresses, rather than any fundamental problem.
Another silicon photonics research area being explored at imec include edge coupling solutions between the waveguide and fibre. “These can have very low insertions losses - one decibel or lower - and can be polarisation insensitive," says Van Campenhout.
Packaging approaches that have a low insertion loss are also being developed, engineered in a way to enable passive alignment assembly procedures. Passively aligning the laser is a key part of reducing component packaging costs. “Silicon doesn’t have a laser so in the next few years it will continue to require hybrid solutions,” says Van Campenhout. “You need a good way to do passive alignment of laser sources, and also packaged in a way that doesn’t require a hermetic solution.”
These are the challenges facing the industry in the next few years: lowering insertion loss and developing packaging technologies. Overcoming these challenges will mark an important milestone since the total market for silicon photonics can be served with a small number of silicon wafers. “In order to drive up volumes, silicon photonics needs to become more competitive at shorter reaches where VCSELs are still the mainstream optical technology,” says Van Campenhout.
It is not yet mature but there is a broader adoption of a model whereby silicon photonics can be designed by one company and fabricated by another
Value proposition
Overall, silicon photonics faces stiff competition from VCSELs and indium phosphide. The two established optical technologies continue to evolve and benefit from having all the optical functionality in one platform, something that silicon photonics, with its lack of a laser source, can’t match.
But the trend whereby the optical transceiver is coming ever closer to the host IC strengthens silicon photonics’ hand. That is because silicon photonics can be co-packaged with silicon, and can share the same equipment as the two device types - electronic and photonic ICs - are put together.
Absil also highlights how the ecosystem needed for widespread adoption of silicon photonics is taking shape. “It is not yet mature but there is a broader adoption of a model whereby silicon photonics can be designed by one company and fabricated by another,” he says. “The adoption of that will result in a new model for the optical component world.”
Market opportunities
Van Campenhout expects silicon photonics to be a niche technology for 100-gigabit connections in the data centre. This may change as silicon photonics matures but today the market is dominated by III-V technologies, he says.
Applications that require integration density in the form of a large number of parallel high-speed transceivers, and close integration with host ICs is what will drive silicon photonics. Imec cites as an example data centre switches which require a large number of network and backplane interconnects tightly integrated with the switch logic IC. These interconnects will be on-board and eventually on-package optical modules. Silicon photonics is ideally placed to provide a scalable I/O solution for such applications, as channel data rates move to 50 gigabit and beyond, says Van Campenhout.
But if it is going to take several years to resolve the insertion loss issues for short-reach interconnects, this is a market application that will only start driving significant volumes early in the next decade.
The advent of 400 Gigabit Ethernet and perhaps 800 Gigabit Ethernet after that will be another driver in the coming years.
Other emerging markets include sensors. “Mid infra-red for sensing is a very interesting topic with quite some potential,” says Van Campenhout. “But it is not entirely clear what will be the killer application.”
Sensing is a fragmented application area where many technology solutions exist. “It is too early to figure out what applications an optical sensing device would be competitive against incumbent designs.” But the more integration required, the more competitive silicon photonics will become for such applications, he says.
The Internet of Things will also use sensing but this will be an extremely cost-sensitive market.
“It is not entirely clear if optical technology will be able to meet such cost pressures but if it does, it will drive tremendous volumes and help develop an ecosystem around silicon photonics,” says Van Campenhout.
Further reading:
Imec gears up for the Internet of Things economy, click here
Graphene prototype modulator shown working at 10 Gigabit
- Imec's graphene electro-absorption modulator works at 10 Gigabit-per-second
- The modulator is small and has be shown to be thermally stable
- Much work is required to develop the modulator commercially
Cross-section of the graphene electro-absorption modulator. The imec work was first detailed in a paper at the IEDM conference held in December 2014 in San Francisco. Source: imec
Imec has demonstrated an optical modulator using graphene operating at up to 10 Gigabit. The Belgium nano-electronics centre is exploring graphene - carbon atoms linked in a 2D sheet - as part of its silicon photonics research programme investigating next-generation optical interconnect. Chinese vendor Huawei joined imec's research programme late last year.
Several characteristics are sought for a modulator design. One is tiny dimensions to cram multiple interfaces in as tight a space as possible, as required for emerging board-to-board and chip-to-chip optical designs. Other desirable modulator characteristics include low power consumption, athermal operation, the ability to operate over a wide range of wavelengths, high speed (up to 50 Gbps) and ease of manufacture.
Imec's interest in graphene stems from the material's ability to change its light-absorbing characteristics over a wide spectral range. "Graphene has a high potential for a wide-band modulator solution and also for an athermal design," says Joris Van Campenhout, programme director for optical I/O at imec.
Source: Gazettabyte
Modulation
For optical modulation, either a material's absorption coefficient or its refractive index is used. Silicon photonics has already been used to implement Mach-Zehnder interferometer and ring resonator modulators. These designs modifying their refractive index and use interference to induce light intensity modulation.
"Mach-Zehnder modulators have been optimised dramatically over the last decade," says Van Campenhout. "They can generate at very high bit rates but they are still pretty big - 1mm or longer - and that prevents further scaling."
Ring resonators are more compact and have been shown working at up to 50 Gigabit. "But they are resonant devices; they are wavelength-specific and thermally dependent," says Van Campenhout. "A one degree change can detune the ring resonance from the laser's wavelength."
The other approach, an electro-absorption modulator, uses an electric field to vary the absorption coefficient of the material and this is the graphene modulator approach imec has chosen.
Electro-absorption modulators using silicon germanium meet the small footprint requirement, have a small capacitance and achieve broadband operation. Capacitance is an important metric as it defines the modulator's maximum data rate as well as such parameters as insertion loss (how many dBs of signal are lost passing through the modulator) and the extinction ratio (a measure of the modulator's on and off intensity).
"Silicon germanium offers a pretty decent modulation quality," says Van Campenhout but the wavelength drifts with temperature. Thermal drift is something that graphene appears to solve.
Imec's graphene electro-absorption modulator comprises a 50 micron graphene-oxide-silicon capacitor structure residing above a silicon-on-insulator rib waveguide. The waveguides are implemented using a 200mm wafer whereas the graphene is grown on a copper substrate before being placed on the silicon die. Van Campenhout refers to the design as hybrid or heterogenous silicon photonics.
The graphene modulator exhibits a low 4dB insertion loss and an extinction ratio of 2.5dB. The device's performance is stable over a broad spectrum: an 80nm window centred around the 1550nm wavelength. The performance of up to 10Gbps was achieved over a temperature range of 20-49°C.
"The key achievement is that we have been able to show that you can operate at 10 Gigabit with very clean modulation eye diagrams," says Van Campenhout. However, much work is needed before the device becomes a viable technology.
Source: Gazettabyte, imec
What next?
Imec has modelled the graphene modulator using a simple resistor-capacitor circuit. "We have been able to identify sources of capacitance and resistance," says Van Campenhout. "We can now better optimise the design for speed or for efficiency."
The speed of the modulator is dictated by the resistance-capacitance product. Yet the higher the capacitance, the greater the efficiency: the better the extinction ratio and the lower the insertion loss. "So it comes down to reducing the resistance," says Van Campenhout. "We think we should be able to get to 25 Gigabit."
With the first prototype, the absorption effect induced by the electric field is achieved between a single graphene plate and the silicon. Imec plans to develop a design using two graphene plates. "If two slabs of graphene are used, we expect to double the effect," says Van Campenhout. "All the charge on both plates of the capacitor will contribute to the modulation of the absorption."
However the integration is more difficult with two plates, and two metal contacts to graphene are needed. "This is still a challenge to do," says Van Campenhout.
Imec has also joined the Graphene Flagship, the European €1 billion programme that spans materials production, components and systems. "One of the work packages is to show you can process on a manufacturing scale graphene-based devices in a CMOS pilot line," he says. Another consideration is to use silicon nitride waveguides rather than silicon ones as these can be more easily deposited.
One challenge still to be overcome is the development of an efficient graphene-based photo-detector. "If this technology is ever going to be used in a real application, there should be a much more efficient graphene photo-detector being developed," says Van Campenhout.