Silicon photonics grapples with 3D packaging demands
Hesham Taha (pictured), CEO of start-up Teramount, is more upbeat about silicon photonics than ever. But, as he outlines, challenges remain.
Hesham Taha is putting in the miles. The CEO of Teramount has been travelling to the East and West to meet with companies.
Termount is working closely with customers and partners adopting its technology that adds fibre to silicon photonics chips.
“We’re shipping units to customers and partners, and we need to be close to them as they integrate our components and address the challenges of integration,” says Taha.
Teramount
For Taha, connecting fibre to a silicon photonics chip inside a pluggable optical transceiver is relatively straightforward.
Far more challenging is when the optical engine and chip are packaged together, known as co-packaged optics. Such a tight coupling raises reliability challenges.
The optical engine is close to the large, heat-generating chip, introducing manufacturing and reliability issues. Also, the fibre-connect to the optical engine inside the package must be scalable. Scaling is key because with each chip generation – whether an AI accelerator or a switch chip – the input-output (I/O) requirements grow.
Teramount’s technology couples the fibre to the silicon photonics chip using a photonic plug and photonic bump.
The photonic plug holds the fibres and couples them to the silicon photonics chip via a photonic bump, a component made during the silicon photonics wafer’s processing.
The photonic bump has two elements: a wideband deflector and a lens mirror for beam expansion. Expanding the light beam enables larger assembly tolerances.
The resulting wafer-level manufacturing may be more complicated, says Taha, but the benefits include relaxed tolerances in the assembly, wideband surface coupling, and the testing of the wafer and the die.
The photonic bump-and-plug combination also enables detachable optics for co-packaged optics designs, benefitting their manufacturing. (For more about Teramount’s technology, click here)
Silicon Photonics meets semiconductor thinking
Taha sees silicon photonics as a platform that enables the integration of optical functions at the wafer scale using standard semiconductor manufacturing techniques.
“It [silicon photonics design] has the same way of thinking as semiconductor people: chip designers, foundries, and packaging people,” says Taha. The result is that silicon photonics is bringing optics to chip design.
The growing maturity of the technology, and the emergence of foundries such as TSMC, GlobalFoundries, Tower Semiconductor, Intel, and ST Microelectronics offering silicon photonics, means that companies with photonic designs can be fabless; a model that has benefitted the chip industry.
Photonic chip designers can use a large foundry’s process design kit (PDK) and send off their silicon photonics designs to be manufactured in volume.
As for co-packaged optics, Taha sees it as a key in the evolution of silicon photonics. Co-package optics is the realisation of silicon photonics whereby optics is integrated next to advanced semiconductor chips.
Industry developments
The growing interest in silicon photonic and co-packaged optics is also evident in some recent announcements, driven by the AI compute scaling needs.
ST Microelectronics unveiled its 300mm wafer PIC100 silicon photonics technology. ST Microelectronics was active in silicon photonics 10 years ago and has returned due to the AI opportunity.
Marvell announced it offers a co-packaged optics solution for accelerator chips to address scale-up networking for AI architectures.
Leading foundry TSMC has outlined its silicon photonics roadmap, which includes co-packaged optics.
And at the GTC 2025 AI developers conference, Nvidia announced it is adding co-packaged optics to its switch platforms for scale-out networking.
“All this is not a surprise because this is where we expected silicon photonics to be one day when we founded the company 10 years ago,” says Taha. “It is just that this day is happening now.”
Teramount sees its fibre attach product as a part of an emerging ecosystem to enable standard semiconductor high-volume manufacturing.
This ecosystem comprises chip designers, foundries, OSATs [outsourced semiconductor assembly and test service providers], and system integrators.
But there are challenges. There may be wafer-scale manufacturing, but issues remain on the integration-packaging side.
“This is why we need to travel, to align with the different partners,” says Taha.
Challenges
Teramount is seeing challenges first-hand given its fibre-attach vantage point. Taha also highlights commercial issues still to be resolved.
The technical challenges revolve around integrating the silicon photonics die with the accompanying lasers and fibres in an advanced package.
Unlike a traditional pluggable optical transceiver, the silicon photonics chip is inserted in a hot environment and must meet operational temperatures of 85oC and even 105oC.
Multiple reflow soldering steps during manufacturing expose the packaging to even higher temperatures (270oC) and thermal stresses.
“These are new technical challenges that silicon photonic chip integration must meet 3D packaging requirements,” says Taha.
3D packaging has requirements that affect the fibre attach. For example, the silicon photonics chip is thinner than the die used in a pluggable if through-silicon via (TSV) technology is used.
TSV refers to the way a vertical electrical connector is done that passes through the die. Any mechanical stresses or warpage impacts the resulting optical performance of the die.
“Co-package optics is creating new challenges when connecting fibre to such thinner chips,” says Taha.
There are also issues with testing a design. “There are still no mature solutions for parallel optical and electrical testing,” says Taha.
The commercial issue he highlights centres around design ownership. With a pluggable module, all the components are delivered in one assembled device with one owner – the module maker.
With co-packaged optics, there are several stages of assembly, with components coming from multiple sources. “Who owns it?” says Taha.
Box system integrators making servers, switches, and the like don’t work with fibre. In contrast, co-packaged optics require connecting and managing hundreds of fibres that fit in a tight space. Good optical coupling and performance are a must to ensure the overall design.
“So this flow [for co-package optics] has yet to be set,” says Taha.
He says all the players, chip designers, foundry packaging vendors (OSATs), and system integrators still need to be aligned. That said, the industry, particularly the large silicon chip vendors, are working to make it happen, says Taha.
This implies that companies such as Nvidia, Intel, AMD, Broadcom, and Marvell are playing a key role here.
Given how the emerging AI opportunity is driving their chip businesses, they have every reason to make this work.
Teramount’s scalable fibre-attach for co-packaged optics
Part 2: Co-packaged optics: fibre-attach
Hesham Taha recently returned from a trip to the US to meet with leading vendors and players serving the silicon photonics industry.
“It is important to continue probing the industry,” says Taha, the CEO of start-up Teramount.
Teramount specialises in fibre assembly technology: coupling fibre to silicon photonics chips.
Taha is now back in the US, this time to unveil Teramount’s latest product at this week’s OFC show being held in San Diego. The company is detailing a new version of its fibre assembly technology, dubbed Teraverse-XD, that doubles the density of fibres connected to a silicon photonics chip.
Teramount is also announcing it is working with GlobalFoundries, a leading silicon-photonics foundry.
Connecting fibre to a silicon photonics device for a pluggable optical module is straightforward. However, attaching fibre to an optical engine for co-packaged optics is challenging. The coupling must be compact and scale to enable even denser connections in future. This is especially true with the co-packaging of future 100-terabit and 200-terabit Ethernet switch chips.
“If I were to describe the last year, it would be aligning our [Teramount] activities to the industry’s evolving needs,” says Taha. “A key part of those needs is being driven by optical activities for AI applications.”
Edge versus surface coupling
Companies are pursuing two main approaches to connecting fibre to a silicon photonics device: surface and edge (side) coupling.
Surface coupling – or its academic term, off-plane coupling – deflects light vertically, away from the chip’s surface. In contrast, edge (in-plane) or side coupling sends the optical waveguide’s light straight through to the fibre at the chip’s edge.
A silicon-photonics grating coupler is used for surface coupling, glancing the light away from the chip’s plane. However, the grating coupler is wavelength-dependent such that the angle of the defection varies with the light.
In contrast, side coupling is wideband. “You can carry multiple wavelengths on each channel,” says Taha. However, side coupling has limited interfacing space, referred to as ‘shoreline density’.
Side coupling is also more complicated to manufacture in volume. Directly bonding the fibre to the chip involves adhesive, and the fibres get in the way of reflow soldering. “It [side coupling] is doable for transceivers, but to make co-packaged optics, side coupling becomes complicated,” says Taha.
Teramount’s approach
Teramount’s approach couples the fibre to the silicon photonics chip using two components: a photonic plug and a photonic bump.
The photonic plug holds the fibres and couples them to the silicon photonics chip via the photonic bump, a component made during the silicon photonics wafer processing. The photonic bump consists of two elements: a wideband deflector and a lens mirror for beam expansion. Expanding the light beam enables much larger assembly tolerances: +/- 30 microns. And across this 60-micron window, only half a dB is lost in misalignment tolerances.
The resulting wafer-level manufacturing may be more complicated, says Taha, but the benefit is relaxed tolerances in the assembly, wide-band surface coupling, and when testing the wafer and the die.
The photonic bump-and-plug combination also enable detachable optics for co-packaged optics designs. This benefits manufacturing and is wanted for co-packaged optics.
Teraverse and Teraverse-XD
There is a clear demarcation between the optics and the switch chip when using pluggables in the data centre. In contrast, co-packaged optics is a system with the optics embedded alongside the chip. A vendor may work with multiple companies to make co-packaged optics, but one product results, with the chip and optical engined co-packaged.
Teramount’s Teraverse solution, using the plug-and-bump combination, brings pluggability to co-packaged optics. The fibres can be attached and detached from the optical engines. “It’s very important to keep that level of pluggability for co-packaged optics,” says Taha.
The approach also benefits manufacturing yield and testing. Separating the fibres from the package protects the fibres during reflow soldering. “Ideally, you want the fibre connected at the last stage and still maintain high level of testability during the packaging process,” says Taha.
Detachable fibre also brings serviceability to co-packaged optics, benefitting for data centre operators.
Teraverse, Teramount’s detachable fiber-to-chip interface, supports single-mode fiber with 125-micron diameter at a 127-micron pitch separation.
Teraverse-XD, announced for OFC, is a follow-on that doubles the fibre density to achieve a near 64-micron pitch. Here, fibres are placed on top of each other, scaling in the Z-dimension. The approach is like how rods or pipes are stored, with the second row of fibres staggered, sitting in the valleys between adjacent fibers in the lower row.
Two rows of photonic bumps are used to couple the light to each row of fibres (see image above). “It’s very important to keep the same real-estate but to have twice the number of fibres,” says Taha.
Future scaling is possible by adding more rows of fibres or by adopting fibres with a smaller pitch.
Teramount’s technology also supports both edge coupling and surface coupling. “We are agnostic,” says Taha. If a co-packaged optics or optical engine vendor wants to use side coupling, it can use the bump-and-plug combination. The bump deflects the beam upwards to the plug packaging which takes the fibres and sends them out horizontally. “We are converting edge coupling to wideband surface coupling,” says Taha. “You don’t need to sacrifice bandwidth to do surface coupling.”
If the vendor wishes to use a grating coupler, Teramount’s bump-and-plug supports that, too, enabling detachable fibering. But here, only the bump’s expanding mirror is used. “For the wideband surface coupling cased, the bump uses two components: the deflector and the expanding mirror,” says Taha.
Both cases are supported by what Teramount refers to as its Universal Photonic Coupler, shown.
Market expectations
Despite being discussed for over a decade, Taha is not surprised that data centre operators have yet to adopt co-packaged optics.
He points out that hyperscalers only want to use co-packaged optics for Ethernet switches once the technology is more mature. They can also keep using a proven alternative: pluggable modules, that continue to advance.
“Hyperscalers are not against the technology, but it is not mature enough,” says Taha. Hyperscalers and systems vendors also want an established supply chain and not proprietary solutions.
To date, Broadcom’s first co-packaged optics switch solution at 25.6-terabit was adopted by Tencent. Broadcom has announced for OFC that it is now delivering its latest 51.2-terabit Bailly co-packaged optics design, backed by ByteDance.
“AI is a different story,” says Taha. “This is the tipping point for a leading vendor to start taking seriously co-packaged optics.”
The advantage of co-packaged optics here is that it accommodates the reach – radix -as well as power savings and improved latency.
Taha expects initial volumes of co-packaged optics sales in 2026.
ECOC 2023 industry reflections
Gazettabyte is asking industry figures for their thoughts after attending the recent ECOC show in Glasgow. In particular, what developments and trends they noted, what they learned and what, if anything, surprised them. Here are the first responses from BT, Huawei, and Teramount.
Andrew Lord, Senior Manager, Optical Networks and Quantum Research at BT
I was hugely privileged to be the Technical Co-Chair of ECOC in Glasgow, Scotland and have been working on the event for over a year. The overriding impression was that the industry is fully functioning again, post-covid, with a bumper crop of submitted papers and a full exhibition. Chairing the conference left little time to indulge in content. I will need to do my regular ECOC using the playback option. But specific themes struck me as interesting.
There were solid sessions and papers around free space optics, including satellite. The activities here are more intense than we would typically see at ECOC. This reflects a growing interest and the specific expertise within the Scottish research community. Similarly, more quantum-related papers demonstrated how quantum is integrating into the mainstream optical industry.
I was impressed by the progress towards 800-gigabit ZR (800ZR) pluggables in the exhibition. This will make for some interesting future design decisions, mainly if these can be used instead of the increasingly ubiquitous 400 gigabit ZR. I am still unclear whether 800-gigabit coherent can hit the required power consumption points for plugging directly into routers. The costs for these plugs, driven by volumes, will have a significant impact.
I also enjoyed a lively and packed rump session debating the invasion of artificial intelligence (AI) into our industry. I believe considerable care is needed, particularly where AI might have a role in network management and optimisation.
Maxim Kuschnerov, Director R&D at Huawei
ECOC usually has fewer major announcements than the OFC show. But ECOC was full of technical progress this time, making the OFC held in March seem a distant memory.
What was already apparent in September at the CIOE in Shenzhen was on full display on the exhibition floor in Glasgow: the linear drive pluggable optics (LPO) trend has swept everyone off their feet. The performance of 100-gigabit native signalling using LPO can not be ignored for single-mode fibre and VCSELs.
Arista gave a technical deep-dive at the Market Focus with a surprising level of detail that went beyond the usual marketing. There was also a complete switch set-up at the Eoptolink booth, and the OIF interop demonstration.
While we must wait for a significant end user to adopt LPO, it begs the question: is this a one-off technological accident or should the industry embrace this trend and have research set its eyes on 200 gigabits per lane? The latter would require a rearchitecting of today’s switches, a more powerful digital signal processor (DSP) and likely a new forward error corrections (FEC) scheme, making the weak legacy KP4 for the 224-gigabit serdes in the IEEE 802.3dj look like a poor choice.
There was less emphasis on Ethernet 1.6 terabits per second (Tb/s) interfaces with 8x200G optical lanes. However, the arrival of a second DSP source with better performance was noted at the show.
The module power of 1.6-terabit DR8 modules showed no significant technological improvement compared with 800Gbps DSP-based modules and looked even more out of place when benchmarking against 800G LPO pluggables. Arista drove home that we can’t continue increasing the power consumption of the modules at the faceplate despite the 50W QSFP-DD1600 announcement.
The same is true for coherent optics.
Although the demonstration of the first 800ZR live modules was technically impressive, the efficiency of the power per bit hardly improved compared to 400ZR, making the 1600ZR project of OIF look like a tremendous technological challenge.
To explain, a symbol rate of 240 gigabaud (GBd) will drive the optics for 1600ZR. Using 240Gbaud with two levels per symbol to create 16QAM over two dimensions is a 400Gbps net rate or 480Gbps gross rate electrical per lane, albeit very short reach. Coherent has four lanes – 2 polarisations & in-phase and quadrature – to deliver four by 400G or 1.6Tbps. This is like what we have now: 200G on the optical side of 1.6T 8x200G PAM4 and 4x200G on 800ZR, while the electrical (longer reach) host still uses 100 gigabits per lane.
The industry will have to analyse which data centre scenarios direct detection will be able to cover with the same analogue-to-digital & digital-to-analogue converters and how deeply coherent could be driven within the data centre.
ECOC also featured optical access evolution. With the 50G FTTx standard completed with components sampling at the show and products shipping next year, the industry has set its eyes on the next generation of very high-speed PON.
There is some initial agreement on the technological choice for 200 gigabits with a dual-lambda non-return to zero (NRZ) signalling. Much of the industry debate was around the use cases. It is unrealistic to assume that private consumers will continue driving bandwidth demand. Therefore, a stronger focus on 6G wireless fronthaul or enterprise seems a likely scenario for point-to-multi-point technology.
Hesham Taha, CEO of Teramount
Co-packaged optics had renewed vigour in ECOC, thanks partly to the recent announcements of leading foundries and other semiconductor vendors collaborating in silicon photonics.
One crucial issue, though, is that scalable fibre assembly remains an unsolved problem that is getting worse due to the challenging requirements of high-performance systems for AI and high-performance computing. These requirements include a denser “shoreline” with a higher fibre count and a denser fibre pitch, and support for an interposer architecture with different photonic integrated component (PIC) geometries.
Despite customers having different requirements for co-packaged optics fibre assembly, detachable fibres now have wide backing. Having fibre ribbons that can be separated from the co-packaged optics packaging process increases manufacturing yield and reliability. It also allows the costly co-packaged optics-based servers/ switches to be serviced in the field ro replace faulty fibre.
Our company, Teramount, had an ECOC demo showing the availability of such a detachable fibre connector for CPO, dubbed Teraverse.
It is increasingly apparent that the solution for a commercially viable fibre assembly on chip lies with a robust manufacturing ecosystem rather than something tackled by any one system vendor. This fabless model has proven itself in semiconductors and must be extended to silicon photonics. This will allow each part of the production chain – IC designers, foundries, and outsourced semiconductor assembly and test (OSAT) players – to focus on what they do best.
Teramount brings pluggability to co-packaged optics
Hesham Taha, the CEO and co-founder of Teramount, describes the last two years for his company as eventful.
“Many things have happened on many fronts,” he says.
Teramount has developed a fibre assembly technology for designs integrating photonics and chips.
The start-up has raised $20 million in funding and has 30 staff. In addition, the company is recruiting staff experienced in manufacturing processes.
“The funding helps to support what we are working on today, which is manufacturing readiness,” says Taha.
Taha also notes marketplace changes as when the rising interest in co-packaged caused some companies that had stepped out of silicon photonics to return.
The marketplace moves reflect silicon photonics’ changing role. The technology is central for integrated designs such as co-packaged optics, whereas before, it had a more peripheral role when used for pluggable optics.
“This is a big change that requires optical integration with electronics, a change in packaging, and how you assemble fibres,” says Taha.
Plugs and bumps
Teramount’s technology coupling fibre to silicon photonics chips has two elements: a photonic bump and a photonic plug. The two combined avoid having to bond the fibre to the chip directly.
This is important for two reasons.
First, fibre bonding is an extra manufacturing step that impacts adversely the yield of an expensive chip.
Second, the plug, which is on a separate plane from the chip, working together with the photonic bump, enables the fibres to be detached and serviced, much like pluggable optics.
The photonic plug holds the fibres using a V-groove mechanism and couples them to the silicon photonics chip via the photonic bump, a component manufactured as part of the silicon photonics design.
It is the plug and bump combined that deliver large assembly tolerances. “The large tolerances is what enables the detachability,” says Taha.
It means a semiconductor company can avoid dealing with fibres and focus on what it does best: designing chips. Foundries and outsourced semiconductor assembly and test (OSAT) companies can handle the wafer-level plug and connect the fibres.
“If the right foundations are set on the silicon photonics wafer, then silicon photonics packaging can become very easy with detachable optics,” says Taha.
Surface coupling and edge coupling
Silicon photonics uses two approaches to couple the optical signal from the fibre to a photonics chip.
One, known as surface coupling, uses a grating coupler, while the second uses side coupling.
Grating couplers are wavelength dependent and send the light beam out at a specific angle. Therefore, changing the wavelength affects the angle, complicating the interfacing.
As part of the silicon photonics chip design, the photonic bump – effectively a lens – is positioned accurately next to the grating coupler.
In contrast, side coupling collects the beam for the silicon photonic chip’s waveguide from the edge of the die. Here, there is no spectral dependency. “You can inject in and out multiple wavelengths,” says Taha.
Teramount says side coupling is not viable for the volume manufacturing of silicon photonic designs.
“You cannot connect a fibre from the edge of the die; you have to prepare for a photonic bump before wafer dicing for side coupling,” says Taha.
Teramount’s design enables light to go to the side of the die, but instead of collecting it from the edge, the photonic bump deflects the beam vertically.
“The photonic bump shifts side coupling into the wideband surface coupling,” says Taha.
The photonic bump has two components in the wideband surface coupling case: a wideband deflector and a lens mirror for beam expansion.
The photonic bump and plug combined forms what Teramount calls self-aligning optics. “You have added more complexity in wafer-level manufacturing, but you have relaxed the tolerances in the assembly domain,” he says.
The resulting design has assembly tolerances of +/- 30 microns. “Altogether, over 60 microns, you lose only half a dB in misalignment tolerances,” he says.
Teramount supports both solutions: surface coupling for a single wavelength and wideband surface coupling for multiple wavelengths. Most customers are working with the wideband solution, says Taha.
The assembly tolerances, wideband surface coupling, and planar separation of the fibres from the die, are what enable fibre detachability, says Taha.
“A technician can manually assemble hundreds of fibres on a co-packaged optics stack,” he says.
The fibre assembly process is compatible with semiconductor packaging techniques. No fibre reflow soldering is needed, improving co-packaged optics’ yield while enabling the servicing of the fibre assembly for co-packaged optics.
Status
Teramount announced in 2022 a collaboration with EV Group, an equipment and process solutions supplier, to tackle wafer-level optics.
Taha says Teramount is working with foundries, OSATs and wafer-level optics manufacturers, such as EV group, to create an ecosystem for its photonic bump and photonic plug technology.
“We want the customer to have the ability to use a foundry to include in their wafer a photonic bump,” says Taha. “Once there, a customer can enjoy the photonic plug connector, its relaxed assembly tolerances, and detachable fibre connectivity.”
Teramount is also working with vendors in networking and computing, developers of co-packaged optics and optical input-output for processor clusters used for machine learning, respectively.
“We’ve already sent samples to customers that we are working with, which includes 32 fibres,” says Taha.
Teramount intends to announce more collaborations with vendors and wafer-manufacturing suppliers.
Packaging silicon photonics using passive alignment
- An Israeli start-up is tackling a key packaging challenge for silicon photonics
Teramount has developed a way to simplify the packaging of silicon photonics chips. Instead of using active alignment whereby an external laser is required to carefully align a fibre to the optical die, the Israeli start-up has developed a technology that allows passive alignment.
Hesham Taha“If we want silicon photonics to ramp up to volume, it has to meet CMOS standards both in terms of fabrication and packaging,” says Hesham Taha, Teramount's CEO.
Taha worked at a company developing atomic force microscopy systems before co-founding Teramount. "We got to know of the problem of injecting light into a waveguide and were surprised that the industry was still using active alignment," he says.
This spurred Taha and a colleague to develop optical solutions to match a single-mode fibre core to an optical waveguide, and they founded Teramount in Jerusalem in 2013. "We started real activity at the beginning of 2015 after getting funding," says Taha.
Existing silicon photonics companies either develop their own customised active alignment equipment or outsource the activity to a third party. "If we solve one of the bottlenecks of silicon photonics in terms of packaging, silicon photonics will be more and more adopted," says Taha.
If we want silicon photonics to ramp up to volume, it has to meet CMOS standards both in terms of fabrication and packaging
The design
Teramount's solution includes two elements: a PhotonicsPlug that is flip-chipped onto the silicon photonics die while still part of a wafer, and a 'bump', a design element added on the silicon photonics chip next to the optical waveguide. "Our solution, which we will be selling, is the PhotonicsPlug and we do require them [the designers] to add one element [the bump] to their silicon photonics chip," says Taha.
The main PhotonicsPlug component is a silicon die comprising optics that manipulates the beam using self-aligning optics and focusses it onto the silicon photonics chip via a glass spacer. Teramount’s die also has V-grooves to interface the single-mode ribbon fibre. Teramount says its die is made using an inexpensive mature CMOS process due to the relatively large feature sizes of the optical elements.
The second design element - the bump - is added next to the silicon photonics chip's grating coupler. The grating coupler is one of two techniques used in the industry to interface a fibre to the waveguide, the other being edge coupling.
“We want to place it [the bump] next to the waveguide so that the optics of the PhotonicPlug works in conjunction with it so that it brings the beam to the waveguide with a large tolerance,” says Taha. The bump is accurately placed on the chip using standard lithography techniques.
The resulting tolerance with which the die can be attached to the silicon photonics wafer is up to ± 20 microns in each of the three dimensions such that standard flip-chip machines can attach the PhotonicsPlug to the wafer.
“Flip-chip machines today work with a tolerance of ± 6 microns and can do 1,500 assemblies per hour,” says Taha.
"This is the main philosophy we are bringing here," he says. "Instead of the accurate placement of the fibre next to the grating coupler which requires active alignment, we want to replace that with a cheaper alignment technique that has much better accuracy at the wafer level," says Taha.
Status
Teramount has already shown working devices using the technology. In addition, Teramount is working with several partners and has demonstrated its technology with their silicon photonics chip designs. "With these partners we are doing the integration and qualifying the performance of the device," says Taha. "We will finalise at least two of these partnerships within a few months."
The start-up is also working to enable volume manufacturing by bringing its technology to industrial fabrication plants. This will be completed in the next few months.
Being a small start-up, the company is focussed on developing the grating coupler solution but it has already started work on an edge-coupling technique to a device’s waveguides. Edge coupling is suited to wavelength-division multiplexing (WDM) silicon photonics chips. That is because grating couplers are wavelength-dependent while edge coupling supports a broader range of wavelengths.