PMC unveils OTN framer for IP core and edge routers
The Meta-240G frames IP router traffic using OTN before passing the traffic to the transport network. Line-rate encryption is included on-chip to secure traffic between data centres and traffic in the cloud.
Source: PMC-Sierra
Adding OTN to a router delivers several benefits, says PMC. OTN helps identify networking faults more quickly and simplifies the monitoring and enforcement of service-level agreements. OTN also includes forward-error correction which benefits optical link performance.
Ethernet is the default router protocol interface while OTN is the dominant protocol in the transport network, says PMC. By moving OTN onto the router’s line port, the transport network extends its end-point reach to the router, says Stephen Docking, senior product line manager, communications unit at PMC. This leads to faster fault isolation and fault recovery.
“The transport network can now communicate with the router in a standard way, providing an extra level of protection that is faster than just IP layer protection,” says Docking.
OTN also supports the monitoring of error rates across the link.“By making the router part of the link, the service provider can not only monitor performance within the transport network but across the entire end-to-end link including the router,” says Docking. Such monitoring helps verify service-level agreements.
Meta-240G features
The Meta-240G is PMC’s third-generation framer for routers. The previous generation device, the 120 gigabit Meta-120G was PMC’s first to support OTU4 100 gigabit frames and was implemented in 40nm CMOS.
The Meta-240G doubles the total bandwidth: 240 gigabit facing the front panel optics and 240 gigabit interfacing to the network processor on the router’s line card. The device can thus support two 100 gigabit interfaces, six 40 gigabit interfaces and 24, 10 gigabit interfaces. “You can even have two 100 Gig and one 40 Gig, or two 100 Gig and four 10 Gig but most customers will just use 100 Gig [interfaces],” says Docking.
PMC has doubled the framer’s capacity while keeping overall power consumption fixed, in effect halving the power per port compared to its previous generation Meta-120G framer. Yet the chip also supports new features including a low-latency AES-256 encryption engine and an on-chip gearbox. The Meta-240G achieves the power savings by making the chip in 28nm CMOS and by improving the serdes design.
The gearbox function translates between 10 gigabit streams and 25 gigabit ones. Many devices use 10 gigabit serdes but to connect to a CFP2 or CFP4 100 gigabit optical modules, 25 gigabit electrical channels are required.
“Designers have had to use discrete gearbox devices [on the line card] which adds space, power and cost,” says Docking. “With the Meta-240G, the gearbox function is integrated into the device.”
Given IP traffic trends, will a 400 gigabit Meta device be needed in 2017? “It may be a bit longer - two to three years’ time - but we would need to [have such a device] to follow the existing trend,” says Docking.
Further information
PMC advances OTN with 400 Gigabit processor, click here
The CFP2 pluggable module gains industry momentum
Finisar and Oclaro unveiled their first CFP2 optical transceiver products at the recent ECOC exhibition in Amsterdam. JDSU also announced that its ONT-100G test equipment now supports the latest 100Gbps module form factor.
Source: Oclaro
The CFP2 is the follow-on module to the CFP, supporting the IEEE 100 Gigabit Ethernet and ITU OTU4 standards. It is half the size of the CFP (see image) and typically consumes half the power. Equipment makers can increase the front-panel port density from four to eight by migrating to the CFP2.
Oclaro also announced a second-generation CFP supporting the 100GBASE-LR4 10km and OTU4 standards that reduces the power consumption from 24W to 16W. The power saving is achieved by replacing a two-chip silicon-germanium 'gearbox' IC with a single CMOS chip. The gearbox translates between the 10x10Gbps electrical interface and the 4x25Gbps signals interfacing to the optics.
The CFP2, in contrast, doesn’t include the gearbox IC.
"One of the advantages of the CFP2 module is we have a 4x25Gbps electrical interface," says Rafik Ward, vice president of marketing at Finisar. "That means that within the CFP2 module we can operate without the gearbox chip." The result is a compact, lower-power design, which is further improved by the use of optical integration.
"That 2.5x faster [interface of the CFP2] equates to about a 6x greater difficulty in signal integrity issues, microwave techniques etc"
Paul Brooks, JDSU
The transmission part of the CFP module typically comprises four externally modulated lasers (EMLs), each individually cooled. The four transmitter optical sub-assemblies (TOSAs) then interface to a four-channel optical multiplexer.
Finisar's CFP2 design uses a single TOSA holding four distributed feedback (DFB) lasers, a shared thermo-electric cooler and the multiplexer. The result of using DFBs and an integrated TOSA is that Finisar's CFP2 consumes just 8W.
Oclaro uses photonic integration on the receiver side, integrating four receiver optical sub-assemblies (ROSAs) as well as the optical demultiplexer into a single design, resulting in a 12W CFP2.
At ECOC, Oclaro demonstrated interoperability between its latest CFP and the CFP2. “It shows that the new modules will talk to existing ones,” says Robert Blum, director of product marketing for Oclaro's photonic components.
Meanwhile JDSU demonstrated its ONT-100G test set that supports the CFP2 and CFP4 MSAs.
"Initially the [test set] applications are focused on those doing the fundamental building blocks [for the 100G CFP2] – chip vendors, optical module vendors, printed circuit board developers," says Paul Brooks, director for JDSU's high speed transport test portfolio. "We will roll out more applications within the year that cover early deployment and production."
The standards-based client-side interfaces is an attractive market for test and measurement companies. For line-side optical transmission, much of the development work is proprietary such that developing a test set to serve vendors' proprietary solutions is not feasible.
The biggest engineering challenge for the CFP2 is its adoption of high-speed 25Gbps electrical interfaces. "The CFP was based on third generation, mature 10 Gig I/O [input/output]," says Brooks. "To get to cost-effective CFP2 [modules] is a very big jump: that 2.5x faster [interface] equates to about a 6x greater difficulty in signal integrity issues, microwave techniques etc."
The company says that what has been holding up the emergence of the CFP2 module has been the 104-pin connector: "The pluggable connector is the big headache," says Brooks. "The expectation is that very soon we should get some early connectors."
The test equipment also supports developers of the higher-density CFP4 module, and other form factors such as the QSFP2.
JDSU will start shipping its CFP2 test equipment in the first quarter of 2013.
Oclaro's second-generation CFP and the CFP2 transceivers are sampling, with volume production starting in early 2013.
Finisar's CFP2 LR4 product will sample in 2012 and enter volume production in 2013.