Mellanox Technologies to acquire EZchip for $811M
Eyal Waldman
Mellanox makes InfiniBand and Ethernet interconnection platforms and products for the data centre while EZchip sells network and multi-core processors that are used in carrier edge routers and enterprise platforms.
EZchip’s customers include Huawei, ZTE, Ericsson, Oracle, Avaya and Cisco Systems.
“Mellanox needs to diversify its business; it is still heavily dependent on the high-performance computing market and InfiniBand,” says Bob Wheeler, principal analyst, networking at market research firm The Linley Group. “EZchip helps move Mellanox into markets and customers that it would not have access to with its existing products.”
CEO Eyal Waldman says Mellanox will continue to focus on the data centre and not the WAN, and that it plans to use EZchip’s products to add intelligence to its designs. Mellanox's Ethernet expertise may also find its way into EZchip’s ICs.
But analysts do expect Mellanox to benefit from telecom. “The big change has to do with Network Function Virtualisation (NFV) and the fact that service provider’s data centres are starting to look more and more like cloud data centres,” says Wheeler. “There is an opportunity for Mellanox to start selling to the large carriers and that is a whole new market for the company.”
Acquiring EZchip
Both companies will ensure continuity and use the same product lines to grow into each other’s markets, said Waldman on a conference call to announce the deal: “Later on will come more combined solutions and products.” First product collaborations are expected in 2016 with more integrated products appearing from 2017.
“Mellanox sees a need to add intelligence to its core products and it does not really have the expertise or the intellectual property,” says Wheeler. One future product of interest is the smart or intelligence network interface controller (NIC). “By working together they could product quite a compelling product,” says Wheeler.
In 2014 EZchip acquired Tilera for $50 million. The value of the deal could have risen to $130 million but was dependent on targets that Tilera did not meet, says Wheeler. Tilera's products include multi-core processors, NICs and white box security appliances. EZchip has also announced the Tile-Mx product family using Tilera’s technology, the most powerful family device will feature 100, 64-bit ARM cores.
The primary application of Tilera’s products is security applications: deep-packet inspection and layer 7 processing. Instead of replacing the general-purpose processor in a security appliance, an alternative approach is to use an intelligent NIC card with a Tilera processor connected via the PCI Express bus to an Intel Xeon-based server. “The card can do a lot of the packet processing offloaded from the Xeon,” says Wheeler.
Another area where EZchip’s NPS processor can be used is in more dedicated appliances or in an intelligent top-of-rack switch. The NPS would perform security as well as terminating overlay protocols used for network virtualisation in the data centre. “You can terminate all those [overlay] protocols in a top-of-rack switch and offload that processing from the server,” says Wheeler.
The key benefit of InfiniBand is its very low latency but the flip side is that the protocol is limited with regard routing to larger fabrics. Adding intelligence could benefit Mellanox’s core Infiniband fabric products, notes Wheeler.
EZchip’s founder and CEO Eli Fruchter said he expects the merger to open doors for EZchip among more hyper-scale data centre players: “With the merger we believe we can be a lot more successful in data centres than by continuing by ourselves.”
Mellanox has made several acquisitions in recent years. It acquired data centre switch fabric player Voltaire in 2011, and in 2013 it added silicon photonics start-up Kotura and chip company IPTronics in quick succession. Now with EZchip's acquisition it will add packet processing and multi-core processor IP to its in-house technology portfolio.
The EZchip acquisition is expected to close in the first quarter of 2016.
Further information:
Mellanox’s Waldman: We've discussed merging for years, click here
EZchip targets multi-core processing with Tilera purchase
Network processor specialist, EZchip Semiconductor, is to acquire Tilera. The deal is valued at $130 million in cash: $50 million when the deal closes, and up to $80 million more depending on performance targets being met.
Bob Wheeler, The Linley Group
Tilera's products include multi-core processors, intelligent network interface cards (NICs) and one rack-unit (1RU) network - 'whitebox' - appliances used for security applications.
Acquiring Tilera will broaden EZchip's market. Tilera's devices are used for network appliances, enterprise routers, cloud computing, video and voice encoders, security, deep-packet inspection, load-balancing, and emerging applications such as software-defined networking (SDN) and network functions virtualisation (NFV).
EZchip's first acquisition will also broaden the company's US presence and customers: Tilera has 100 customers including Brocade, Check Point Software Technologies, Cisco, Fujitsu, Harmonic, MikroTik and ZTE.
EZchip estimates that with the acquisition, its total addressable market will double to $2 billion by 2016.
EZchip's flagship NPS is a high-end network processor family while Tilera's multi-core general processors include the Tile-GX family with 9, 16, 36 and 72, 64-bit cores, programmed using the C-language and which supports the Linux operating system.
"The two companies are highly complementary," says Bob Wheeler, principal analyst for networking at the Linley Group. "Beyond the obvious addition of products, markets, and customers, I see Tilera’s software and systems expertise as important to the success of EZchip’s existing NPS programme."
Eli Fruchter, CEO of EZchip, says that the two companies have been discussing co-development of a next-generation multi-core family that will add specialist networking accelerator hardware from EZchip. The resulting family will have the highest core count at the lowest power, while achieving leading networking and packet-processing performance, says the CEO.
Tilera's designs are noted for their processing performance per watt. Wheeler also highlights the company's iMesh tiled architecture which enables efficient scaling as cores are added to a chip. "Tilera’s proprietary 64-bit VLIW [very long instruction word] CPU design is also important in delivering leading power efficiency," he says.
The next-generation device family will use a standard processing core and move away from Tilera's proprietary technology. EZchip's NPS uses the 32-bit ARC core which EZchip has redesigned. "Network security and monitoring are the primary targets [for the next-gen devices]," says Wheeler. "Tilera currently serves other applications, including videoconferencing, but these won’t benefit from EZchip’s accelerators."
Tilera's revenues were $35 million in 2013, suggesting single-digit percent market share using EZchip's $1 billion TAM estimate. It thus has some way to go to compete with Broadcom and Cavium. Near term, customers may be more willing to work with a profitable public company, notes Wheeler, but for EZchip to achieve major share gains will depend on delivering next-generation processors.
Tilera's revenues declined in the first half of 2014. EZchip would not detail why, except to suggest that the decline in orders is temporary and that growth will return in the second half of 2014. EZchip is confident Tilera's revenues will exceed $35 million in 2015.
EZchip will pay Tilera's shareholders up to $80 million if revenue targets are met: $50 million in cash if revenues reach $45 million between when the deal closes in Q3 2014 and June 2015, and a further $30 million if revenues of $31 million are achieved in the second half of 2015.
Network processors to support multiple 100 Gigabit flows
“We don’t know of any device, announced at least, that comes close to this”
Amir Eyal, EZchip
The NP-5 is noteworthy in integrating within a single chip a full-duplex 100 Gigabit-per-second (Gbps) packet processor and traffic manager. Such integration is important as line cards move from 100Gbps to 400Gbps densities, says Bob Wheeler, senior analyst at The Linley Group.
Target markets
The NP-5 is aimed at router and transport switches platforms that make up the carrier Ethernet switch router (CESR) market. Platforms include packet optical transport switches and edge routers. Infonetics Research forecasts that the total Carrier Ethernet market will grow to US $37bn in 2015 from $26bn in 2010, while the CESR market will double to $20bn by 2015.
EZchip says its main competition is in-house ASIC design teams of the large system vendors. Alcatel-Lucent for example has just announced its FP3 400Gbps network processor. The FP3 is implemented as a three-device chipset made up of a packet processor, traffic manager and a fabric-access chip.
EZchip also believes the device has a role within the data centre. New protocol developments require packet processing that today can only be achieved using a packet processor, it says.
An example is OpenFlow which EZchip supports using its current NP-4 processor. OpenFlow is an academic initiative that allows networking protocols to be explored on existing switch hardware but it is of growing interest to data centre operators. The initiative creates an industry-standard application programming interface (API) to the underlying switch platforms.
The latest OpenFlow version (V1.1) can only be supported using a network processor, says Amir Eyal, EZChip’s vice president of business development. However the data centre is seen as a secondary market for the NP-5. The downside is that the NP-5 and similar network processors targeted at telecoms cost more than switch ASICs from vendors. Only when the functionality of an NPU is needed will vendors pay more.
NP-5 architecture
The chip's main functional blocks are a programmable packet processor and a traffic manager. Also integrated on-chip is an integrated Ethernet switch fabric adaptor, media access controllers (MACs) that support 1, 10, 40 and 100 Gigabit Ethernet (GbE), and a memory controller designed for use with DDR3 external memory to reduce overall system cost. The current NP-4 supports DDR3 and RLDRAM - considerably more expensive than DDR3.
The packet processing is performed using task-optimised processor engines (TOPs). Four styles of TOP engines are used: Two perform classification - parsing, which extracts packet headers and data fields, and searching using look-up tables; and one TOP each for packet modification and packet forwarding.
Each TOP has a 64-bit architecture and processes a single thread. A scheduler allocates a packet to the next available free TOP. EZchip does not disclose the number of TOPs it uses but says that the NP-5 will have almost twice the number used for the NP-4, with the most numerous being the search TOP due to the numerous look-ups needed.
An on-chip ternary content addressable memory (TCAM), meanwhile, supports more sophisticated look-ups and operates in parallel to the simpler TOPs-based searches.
The traffic manager provides bandwidth and guarantees a certain service level performance to particular packet flows. The traffic manager makes decisions when packet congestion occurs based on a given traffic’s priority and its associated rules.
The NP-5 first stores packets in its internal buffer memory before dropping lower-priority packets once memory is full. It is rare that all the input ports are full simultaneously. By taking advantage of the integrated MACs on-chip, up to 24, 10 Gigabit ports can be used to input data. The NP-5 can thus support peak flows of 240Gbps, or a 2.4-to-1 oversubscription rate, equating to a system line card supporting 24-ports at 10Gbps traffic at the same cost as a 10 port-10Gbps design, says EZchip.
The NP-5 will also have four integrated engines. Each engine will support either 12x10GbE, 3x40GbE, 1x100GbE or one Interlaken interface. Two of the four interface engines support 48, 1GbE ports using the QSGMII interface while the remaining two support 12x1GbE ports using the SFI interface.
The QSGMII interface allows a quadrupling of the links by interleaving four ports per link. However an additional external device is needed to break the four interleaved ports into four separate ones. The SFI interface allows a direct connection to a 1GbE optical module.
Also included on the device is an Ethernet fabric adapter that supports 24, 10Gbps (10GBASE-KR) short-reach backplane interfaces.
Device metrics
The 200Gbps NP-5 will be able to process up to 300 million 64byte packets per second. The chip’s power consumption is estimated at 50W. Implemented using a 28nm CMOS process, the device will require 2,401 pins.
What next?
The NP-5 is scheduled to sample year-end 2012. Assuming it takes 18 months to design systems, it will be mid-2014 when NP-5 line cards supporting multiple 100Gbps interfaces are first deployed. EZchip says four or even eight NP-5s could be integrated on a line card, achieving a total packet throughput of 1.6Tbit/s per board.
Meanwhile EZchip’s NP-4 is currently sampling and will ramp in the next few months. Most of the large edge router and switch vendors are designing the NP-4 into their systems, says EZchip.
Further reading:
For more NP-5 detail see the New Electronics article, click here.